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publication number s71pl-jb0_00 revision a amendment 0 issue date april 21, 2005 s71pl127jb0/s71pl129jb0/s71pl064jb0 with psram type 2, rev d based mcps stacked multi-chip product (mcp) flash memory and ram 128/64 megabit (8/4m x 16-bit) cmos 3.0 volt-only simultaneous operation page mode flash memory and 32 megabit (2m x 16-bit) static ram/pseudo static ram data sheet advance information notice to readers: the advance information status indicates that this document contains information on one or more products under development at spansion llc. the information is intend ed to help you evaluate this product. do not design in this product without contacting the factory. spansion llc reserves the right to change or discon tinue work on this proposed product without notice.
ii s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information notice on data sheet designations spansion llc issues data sheets with advance info rmation or preliminary designations to advise readers of product information or intended specif ications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion data sheet designations are presented here to high - light their presence and definitions. advance information the advance information designation indicates that spansion llc is developing one or more spe - cific products, but has not committed any design to production. information presented in a doc - ument with this designation is likely to change, and in some ca ses, development on the product may discontinue. spansion llc therefore places the following conditions upon advance informa - tion content: ?this document contains information on one or more products under development at spansion llc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion llc reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod - uct life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a pr eliminary document should be expected while keeping these as - pects of production under consideration. spansion places the following conditions upon prelimi - nary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document m ay be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of pr oducts with different designations (advance in - formation, preliminary, or full pr oduction). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc charac teristics table and ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option , temperature range, package type, or v io range. changes may also include those needed to clarify a descript ion or to correct a typographical error or incor - rect specification. spansion llc applies the follo wing conditions to docu ments in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion llc deems the produc ts to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local amd or fujitsu sales office.
this document states the current technical specifications regard ing the spansion product(s) described herein. each product desc ribed herein may be designated as ad- vance information, preliminary, or full production. see the section ?notice on data sheet designations? for definitions. publication number s71pl-jb0_00 revision a amendment 0 issue date april 21, 2005 distinctive characteristics mcp features ? power supply voltage of 2.7 v to 3.1 v ? high performance ? 65 ns (65 ns flash, 70 ns psram) ? packages ? 7 x 9 x 1.2mm 56 ball fbga ? 8 x 11.6 x 1.2mm 64 ball fbga ? operating temperature ? ?25c to +85c ? ?40c to +85c general description the s71pl series is a product line of stacked multi-chip product (mcp) packages and consists of: ? one s29pl129j, s29pl127j or s29pl064j flash memory die ? one psram type 2, rev d die the products covered by this docume nt are listed in the table below: s71pl127jb0/s71pl129jb0/s71pl064jb0 with psram type 2, rev d based mcps stacked multi-chip product (mcp) flash memory and ram 128/64 megabit (8/4m x 16-bit) cmos 3.0 volt-only simultaneous operation page mode flash memory and 32 megabit (2m x 16-bit) static ram/pseudo static ram data sheet advance information flash memory density pl064j pl127j pl129j psram density s71pl064jb0 s71pl127jb0 s71pl129jb0
2 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information product selector guide 64mb flash memory 128mb flash memory device-model# flash access time (ns) (p)sram density (p)sram access time (ns) package s71pl064jb0-qb 65 32m psram 70 tlc056 device-model# flash access time (ns) psram density psram access time (ns) package s71pl127jb0-qb 65 32m psram 70 tla064 s71pl129jb0-qb 65 32m psram 70 tla064
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 3 advance information s71pl127jb0/s71pl129jb0/s71pl064jb0 with psram type 2, rev d based mcps distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ........................................................................................................ 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 64mb flash memory .............................................................................................2 128mb flash memory ...........................................................................................2 connection diagram (s71pl064j) . . . . . . . . . . . . . .6 connection diagram (s71pl127j) . . . . . . . . . . . . . .7 connection diagram (s71pl129j) . . . . . . . . . . . . . .8 special handling instructions for fb ga package ...................................8 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering information . . . . . . . . . . . . . . . . . . . . . . . 10 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12 tlc056?56-ball fine-pit ch ball grid array (fbga) 9 x 7mm package ................................................................................. 12 tsc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package ..................................................................................13 tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6mm package ............................................................................. 14 tsb064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ............................................................................15 s29pl-j general description . . . . . . . . . . . . . . . . . . . . . . . 18 simultaneous read/write operation with zero latency ...................... 18 page mode features ........................................................................................... 18 standard flash memory features ..... .............................................................. 19 product selector guide . . . . . . . . . . . . . . . . . . . . 20 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 simultaneous read/write block diagram . . . . . 21 simultaneous read/write block diagram (pl129j) . . . . . . . . . . . . . . . . . . . . . . . . . 22 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 device bus operations . . . . . . . . . . . . . . . . . . . . . 24 table 1. pl127j device bus operations ................................ 24 table 2. pl129j device bus operations ................................ 24 requirements for reading array data ........................................................ 24 random read (non-page read) ...... ..........................................................25 page mode read ..............................................................................................25 table 3. page select .......................................................... 25 simultaneous read/write operation ...........................................................25 writing commands/command sequences ................................................ 26 accelerated program operation ..... ......................................................... 26 autoselect functions .................................................................................... 26 standby mode ...................................................................................................... 26 automatic sleep mode ......................................................................................27 reset#: hardware reset pin ........... ..............................................................27 output disable mode ........................................................................................27 table 4. pl127j sector architecture ..................................... 28 table 5. pl064j sector architecture ..................................... 35 table 6. pl032j sector architecture ..................................... 38 table 7. s29pl129j sector architecture ............................... 40 table 8. secured silicon sector addresses ............................ 46 autoselect mode ................................................................................................ 46 table 9. autoselect codes (high voltage method) .................. 47 table 10. autoselect codes for pl129j .................................. 47 table 0.2. pl127j boot sector /sector block addresses for protection/unprotection ...................................................... 48 table 11. pl129j boot sector /sector block addresses for protection/unprotection ...................................................... 49 table 12. pl064j boot sector /sector block addresses for protection/unprotection ...................................................... 50 table 13. pl032j boot sector /sector block addresses for protection/unprotection ...................................................... 51 selecting a sector protection mode .............................................................. 51 table 14. sector protection schemes ................................... 52 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . 52 persistent sector protection ......... .................................................................. 52 password sector protection ............. .............................................................. 52 wp# hardware protection ............................................................................. 52 selecting a sector protection mode ............................................................. 52 persistent sector protection . . . . . . . . . . . . . . . . 52 persistent protection bit (ppb) ...................................................................... 53 persistent protection bit lock (ppb lock) ................................................. 53 dynamic protection bit (dyb) ....................................................................... 53 persistent sector protection mode locking bit ....................................... 54 password protection mode . . . . . . . . . . . . . . . . . 55 password and password mode locking bit ................................................ 55 64-bit password .................................................................................................. 55 write protect (wp#) ....................................................................................... 56 persistent protection bit lock . .................................................................. 56 high voltage sector protection ... .................................................................. 56 figure 1. in-system sector protection/sector unprotection algorithms........................................................................ 57 temporary sector unprotect .......... .............................................................. 57 figure 2. temporary sector unprotect operation ................... 58 secured silicon sector flash memor y region ...........................................58 factory-locked area (64 words) ..............................................................58 customer-lockable area (64 words) ...................................................... 59 secured silicon sector protection bits .................................................... 59 figure 3. secured silicon sector protect verify ...................... 59 hardware data protection ............... ..............................................................60 low vcc write inhibit ................................................................................60 write pulse ?glitch? protection ...............................................................60 logical inhibit ...................................................................................................60 power-up write inhibit ...............................................................................60 common flash memory interface (cfi) . . . . . . 60 table 15. cfi query identification string .............................. 61 table 16. system interface string ........................................ 61 table 17. device geometry definition ................................... 61 table 18. primary vendor-specific extended query ................ 62 command definitions . . . . . . . . . . . . . . . . . . . . . 63 reading array data ........................................................................................... 63 reset command .................................................................................................64 autoselect command sequence .......... ..........................................................64 enter secured silicon sect or/exit secured silicon sector command sequence ............................................................................ 65 word program command sequence . .......................................................... 65 unlock bypass command sequence .. ...................................................... 65 figure 4. program operation ............................................... 66 chip erase command sequence ................................................................... 66 sector erase command sequence ................................................................ 67 figure 5. erase operation ................................................... 68 erase suspend/erase resume comma nds ..................................................68 program suspend/program resume commands ......................................69 command definitions . . . . . . . . . . . . . . . . . . . . . 70
4 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information table 0.3. memory array command definitions ..................... 70 table 0.4. sector protection command definitions ................. 72 write operation status . . . . . . . . . . . . . . . . . . . . 73 dq7: data# polling ............................................................................................73 figure 6. data# polling algorithm......................................... 75 ry/by#: ready/busy# .......................................................................................75 dq6: toggle bit i ................................................................................................76 figure 7. toggle bit algorithm.............................................. 77 dq2: toggle bit ii ...............................................................................................77 reading toggle bits dq6/dq2 ......................................................................77 dq5: exceeded timing limits ....................................................................... 78 dq3: sector erase timer ................... ............................................................. 78 table 19. write operation status ......................................... 79 absolute maximum ratings . . . . . . . . . . . . . . . . . 80 figure 8. maximum overshoot waveforms............................. 80 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 80 industrial (i) devices ......................................................................................... 80 extended (e) devices .... .................................................................................... 80 supply voltages ................................................................................................... 80 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81 table 20. cmos compatible ................................................ 81 ac characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 82 test conditions .................................................................................................. 82 figure 9. test setups.......................................................... 82 table 21. test specifications ............................................... 82 switching waveforms ........................................................................................83 table 22. key to switching waveforms ................................ 83 figure 10. input waveforms and measurement levels............. 83 vcc ramprate ...................................................................................................83 read operations ................................................................................................ 84 table 23. read-only operations .......................................... 84 figure 11. read operation timings ....................................... 85 figure 12. page read operation timings ............................... 85 reset ...................................................................................................................... 86 table 24. hardware reset (reset#) .................................... 86 figure 13. reset timings..................................................... 86 erase/program operations ............................................................................. 87 table 25. erase and program operation ............................... 87 timing diagrams ................................................................................................. 88 figure 14. program operation timings .................................. 88 figure 15. accelerated program timing diagram .................... 88 figure 16. chip/sector erase operation timings ..................... 89 figure 17. back-to-back read/write cycle timings ................. 89 figure 18. data# polling timings (during embedded algorithms) ............................................ 90 figure 19. toggle bit timings (during embedded algorithms) .. 90 figure 20. dq2 vs. dq6 ...................................................... 91 protect/unprotect . . . . . . . . . . . . . . . . . . . . . . . . 91 table 26. temporary sector unprotect ................................. 91 figure 21. temporary sector unprotect timing diagram ......... 91 figure 22. sector/sector block protect and unprotect timing diagram ........................................................................... 92 controlled erase operations ........... ..............................................................92 table 27. alternate ce# controlled erase and program operations ........................................................... 92 figure 23. alternate ce# controlled write (erase/program) operation timings ............................................................. 93 table 28. ce1#/ce2# timing (s29pl129j only) .................... 93 figure 24. timing diagram for alternating between ce1# and ce2# control ..................................................... 93 table 29. erase and programming performance ..................... 94 type 2 psram d-die features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 96 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 96 power up ..............................................................................................................96 figure 25. power up 1 (cs1# controlled) ............................. 96 figure 26. power up 2 (cs2 controlled)................................ 97 functional description . . . . . . . . . . . . . . . . . . . . . 97 absolute maximum ratings . . . . . . . . . . . . . . . . 98 dc recommended operating conditions . . . . . 98 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 dc and operating characteristics . . . . . . . . . . . 99 ac operating conditions . . . . . . . . . . . . . . . . . . 99 test conditions (test load and test input/output reference) ......... 99 figure 27. output load ...................................................... 99 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 100 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 101 read timings ........................................................................................................101 figure 28. timing waveform of read cycle(1) ..................... 101 figure 29. timing waveform of read cycle(2) ..................... 101 figure 30. timing waveform of page cycle (page mode only) 102 write timings .....................................................................................................102 figure 31. write cycle #1 (we# controlled)........................ 102 figure 32. write cycle #2 (cs1# controlled) ...................... 103 figure 33. timing waveform of write cycle(3) (cs2 controlled) ............................................................. 103 figure 34. timing waveform of write cycle(4) (ub#, lb# controlled) ..................................................................... 104 revision summary
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 5 advance information mcp block diagram v ss reset# flash 1 io 15 -io 0 v cc f dq 15 to dq 0 ry/by# wp#/acc v cc v cc ce#f1 flash-only address shared address oe# we# v ccs v cc ce#s ub#s lb#s ce# ub# lb# psram/sram ce2 ce2# (available only on pl129j)
6 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information connection diagram (s71pl064j) notes: 1. a20 is shared for the 32m psram configuration. 2. connecting all vcc and vss balls to vcc and vss is recommended. mcp flash-only addresses shared addresses s71pl064jb0 a21 a20-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 a21 e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 7 advance information connection diagram (s71pl127j) notes: 1. a20 is shared for the 32m psram and above configurations. 2. connecting all vcc & vss balls to vcc & vss is recommended. 3. ball l5 will be vccf in the 84-ball density upgr ades. do not connect to vss or any other signal. mcp flash-only addresses shared addresses s71pl127jb0 a22-a21 a20-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d 4 e 6 ce2s a20 j6 dq4 k6 vccs rfu d 6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d 7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e 9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f h6 h5 b6 b5 ram only shared (note 1) flash only legend reserved fo r future use rfu rfu* l6 l5 lb# c 4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc *see notes below 64-ball fine-pitch ball grid array (top view, balls facing down)
8 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information connection diagram (s71pl129j) notes: 1. a20-a0 is shared between the flash and psra m, while a21 and ce2#f are flash-only signals. 2. connecting all v cc and v ss balls to v cc and v ss is recommended. 3. ball l5 is v ccf in the 84-ball density upgrades. do not connect to v ss or any other signal. 4. ball f9 is ce2# in an s71pl129jb0, wh ile ball h2 is ce1# in an s71pl129jb0. special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultra- sonic cleaning methods. the package and/ or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged peri- ods of time. e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d4 e6 ce2s a20 j6 dq4 k6 vccs rfu d6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e9 f9 a21 g9 ce2#f h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce1#f h6 h5 b6 b5 ram only shared (note 1) flash only legend reserved fo r future use rfu rfu* l6 l5 lb# c4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc *see notes below 64-ball fine-pitch ball grid array (top view, balls facing down)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 9 advance information pin description a21?a0 = 22 address inputs (common) dq15?dq0 = 16 data inputs/outputs (common) ce1#f = chip enable 1 (flash) ce2#f = chip enable 2 (flash) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output (flash 1) ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low (flash 1) wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce1#f oe# we # reset# r y/by# wp#/acc ub# ce2#f ce2ps ce1#ps lb#
10 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ordering information the order number is formed by a va lid combinations of the following: s71pl 129 j b0 ba w qb 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number see the valid combinations table. temperature range w = wireless (-25 c to +85 c) i = industrial (-40 c to +85 c) package type ba = fine-pitch bga lead (pb)-free compliant package bf = fine-pitch bga lead (pb)-free package psram density b0 = 32mb psram process technology j = 110 nm, floating gate technology flash density 129 = 128mb with 2 ce# 127 = 128mb 064 = 64mb product family s71pl multi-chip product (mcp) 3.0-volt simultaneous read/write, page mode flash memory and ram s71pl064j valid combinations flash speed options (ns) (p)sram type/ access time (ns) package marking base ordering part number package & temperature package modifier/ model number packing type s71pl064jb0 baw, bfw bai, bfi qb 0, 2, 3 (note 1) 65 psram2 rev d die (note 2) s71pl127j valid combinations flash speed options (ns) (p)sram type/ access time (ns) package marking base ordering part number package & temperature package modifier/model number packing type s71pl127jb0 baw, bfw bai, bfi qb 0, 2, 3 (note 1) 65 psram2 rev d die (note 2) notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations. notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 11 advance information s71pl129j valid combinations flash speed options (ns) (p)sram type/ access time (ns) package marking base ordering part number package & temperature model number packing type s71pl129jb0 baw, bfw bai, bfi qb 0, 2, 3 (note 1) 65 psram2 rev d die (note 2) notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
12 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information physical dimensions tlc056?56-ball fine-pitch ball gr id array (fbga) 9 x 7mm package 3348 \ 16-038.22a package tlc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 13 advance information tsc056?56-ball fine-pitch ball grid array (fbga) 9 x 7mm package 3427 \ 16-038.22 package tsc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
14 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information tla064?64-ball fine-pitch ball gr id array (fbga) 8 x 11.6mm package 3352 \ 16-038.22a package tla 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10, f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.20 c 0.08 c b 64x 6 0.08 m c 0.15 m c a b a2 a a1 side view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 15 advance information tsb064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3351 \ 16-038.22a package tsb 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 017 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10 f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c c 0.08 a1 b 64x 0.15 m c a b 0.08 m c 6 side view 7 se e1 corner pin a1 a c db d1 a 10 ed 9 8 6 5 3 ee 2 4 7 e d 0.15 c (2x) gfe k jh sd 7 m l 1 c c 0.15 b (2x) 0.20 10 pin a1 corner index mark a2 a top view bottom view
publication number s71pl-jb0_00 revision a amendment 0 issue date april 21, 2005 distinctive characteristics architectural advantages ? 128/128/64/32 mbit page mode devices ? page size of 8 words: fast page read access from random locations within the page ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read, erase, and program operations for ba ttery-powered applications ? dual chip enable inputs (only in pl129j) ? two ce# inputs control sele ction of each half of the memory space ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations ? flexbank architecture (pl127j/pl064j/pl032j) ? 4 separate banks, with up to two simultaneous operations per device ?bank a: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ?bank b: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ?bank c: pl127j - 48 mbit (32 kw x 96) pl064j - 24 mbit (32 kw x 48) pl032j - 12 mbit (32 kw x 24) ?bank d: pl127j -16 mbit (4 kw x 8 and 32 kw x 31) pl064j - 8 mbit (4 kw x 8 and 32 kw x 15) pl032j - 4 mbit (4 kw x 8 and 32 kw x 7) ? flexbank architecture (pl129j) ? 4 separate banks, with up to two simultaneous operations per device ? ce#1 controlled banks: bank 1a: pl129j - 16mbit (4kw x 8 and 32kw x 31) bank 1b: pl129j - 48mbit (32kw x 96) ? ce#2 controlled banks: bank 2a: pl129j - 48 mbit (32kw x 96) bank 2b: pl129j - 16mbit (4kw x 8 and 32kw x 31) ? enhanced versatilei/o tm (v io ) control ? output voltage generated and input voltages tolerated on all control inpu ts and i/os is determined by the voltage on the v io pin ?v io options at 1.8 v and 3 v i/o for pl127j and pl129j devices ?3v v io for pl064j and pl032j devices ? secured silicon sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words ? both top and bottom boot blocks in one device ? manufactured on 110 nm process technology ? data retention: 20 years typical ? cycling endurance: 1 million cycles per sector typical performance characteristics ? high performance ? page access times as fast as 20 ns ? random access times as fast as 55 ns ? power consumption (typical values at 10 mhz) ? 45 ma active read current ? 17 ma program/erase current ? 0.2 a typical standby mode current software features ? software command-set compatible with jedec 42.4 standard ? backward compatible with am29f, am29lv, am29dl, and am29pdl families and mbm29qm/rm, mbm29lv, mbm29dl, mbm29pdl families ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank ? program suspend / program resume ? suspends a program operation to allow read operation from sectors ot her than the one being programmed s29pl-j 128/128/64/32 megabit (8/8/4/2 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory with enhanced versatileio tm control data sheet advance information
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 17 advance information ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp#/ acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password ? package options ? standard discrete pinouts 11 x 8 mm, 80-ball fine-pitch bga (pl127j) (vbg080) 8.15 x 6.15 mm, 48-ball fine pitch bga (pl064j/ pl032j) (vbk048) ? mcp-compatible pinout 8 x 11.6 mm, 64-ball fine-pitch bga (pl127j) 7 x 9 mm, 56-ball fine-pitch bga (pl064j and pl032j) compatible with mcp pinout, allowing easy integration of ram into existing designs ? 20 x 14 mm, 56-pin tsop (pl127j) (ts056)
18 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information general description the s29pl-j is a 128/128/64/32 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device organized as 8/8/4/2 mwords. the devices are offered in the following packages: ? 11mm x 8mm, 80-ball fine-pitch bga standalone (pl127j) ? 8mm x 11.6mm, 64-ball fine-pitch bg a multi-chip compatible (pl127j) ? 8.15mm x 6.15mm, 48-ball fine-pitch bga standalone (pl064j/pl032j) ? 7mm x 9mm, 56-ball fine-pitch bga mult i-chip compatible (pl064j and pl032j) ? 20mm x 14mm, 56-pin tsop (pl127j) the word-wide data (x16) appears on dq15-dq0. this device can be programmed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separa te chip enable (ce#), write enable (we#) and output enable (oe#) controls. note: device pl12 9j has 2 chip enable inputs (ce1#, ce2#). simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be consider ed to be four separate memory arrays as far as certain operations are concerned. the device can improve overall system performance by al- lowing a host system to program or erase in on e bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. the device can be organized in both top and bo ttom sector configurations. the banks are orga- nized as follows: page mode features the page size is 8 words. after initial page access is accomplish ed, the page mode operation pro- vides fast read access speed of ra ndom locations wi thin that page. table 1: bank pl127j sectors pl064j sectors pl032j sectors a 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7) b 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) c 48 mbit (32 kw x 96) 24 mbit (32 kw x 48) 12 mbit (32 kw x 24) d 16 mbit (4 kw x 8 and 32 kw x 31) 8 mbit (4 kw x 8 and 32 kw x 15) 4 mbit (4 kw x 8 and 32 kw x 7) table 2: bank pl129j sectors ce# control 1a 16 mbit (4 kw x 8 and 32 kw x 31) ce1# 1b 48 mbit (32 kw x 96) ce1# 2a 48 mbit (32 kw x 96) ce2# 2b 16 mbit (4 kw x 8 and 32 kw x 31) ce2#
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 19 advance information standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . commands are written to the command re gister using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. the unlock bypass mode facilitates faster programming times by requ iring only two write cycles to program data in- stead of four. device erasure occurs by executing the erase command sequence. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been com- pleted, the device is ready to read array data or accept another command. the sector erase architecture allows memory se ctors to be erased and reprogrammed without af- fecting the data contents of ot her sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automa tically inhibits write operations during power transitions. the hardware sector protection feature disables both pro- gram and erase operations in any combination of sectors of memory. this can be achieved in- system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, an y sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secured silicon sector area (one time program area) after an erase suspend , then the user must use the proper command sequence to enter and exit this region. the program suspend/program resume feature enables the user to hold the program oper- ation to read data from any sector that is not se lected for programming. if a read is needed from the secured silicon sector area, persistent protec tion area, dynamic protection area, or the cfi area, after a program suspend, then the user mu st use the proper command sequence to enter and exit this region. the device offers two power-saving features. wh en addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power consumptio n is greatly reduced in both these modes. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunnel- ing. the data is programmed using hot electron injection.
20 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information product selector guide note: contact factory for availability block diagram notes: 1. ry/by# is an open drain output. 2. amax = a22 (pl127j), a21 (pl129j and pl064j), a20 (pl032j). 3. for pl129j there are two ce# (ce1# and ce2#). part number s29pl032j/s29pl064j/s29pl-j/s29pl129j speed option v cc ,v io = 2.7?3.6 v 55 (note) 60 65 70 v cc = 2.7?3.6 v, v io = 1.65?1.95 v (pl127j and pl129j only) 65 70 max access time, ns (t acc ) 55 (note) 60 25 65 70 70 max ce# access, ns (t ce ) max page access, ns (t pacc ) 20 (note) 25 25 30 30 max oe# access, ns (t oe ) v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) amax?a3 a2?a0 ce# we# dq15?dq0 v io oe#
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 21 advance information simultaneous read/write block diagram note: amax = a22 (pl127j), a21 (pl064j), a20 (pl032j). v cc v ss bank a address bank b address amax?a0 reset# we# ce# dq0?dq15 state control & command register ry/by# bank a x-decoder oe# dq15?dq0 status control amax?a0 amax?a0 a22?a0 a22?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank b x-decoder y-gate bank c x-decoder bank d x-decoder y-gate bank c address bank d address wp#/acc
22 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information simultaneous read/write block diagram (pl129j) note: amax = a21 (pl129j). v cc v ss bank 1a address bank 1b address a21?a0 reset# we# ce1# dq0?dq15 ce2# state control & command register ry/by# bank 1a x-decoder oe# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1#=l ce2#=h ce1#=h ce2#=l wp#/acc
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 23 advance information pin description amax?a0 = address bus dq15?dq0 = 16-bit data inputs/outputs/float ce# = chip enable inputs oe# = output enable input we# = write enable v ss = device ground nc = pin not connected internally ry/by# = ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. wp#/acc = write protect/acceleration input. when wp#/acc= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp#/ acc= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp#/acc= 12v, program and erase operations are accelerated. v io = input/output buffer power supply (1.65 v to 1.95 v (for pl127j and pl129j) or 2.7 v to 3.6 v (for all plxxxj devices)) v cc =chip power supply (2.7 v to 3.6 v or 2.7 to 3.3 v) reset# = hardware reset pin ce1#, ce2# = chip enable inputs. ce1# controls the 64mb in banks 1a and 1b. ce2# controls the 64 mb in banks 2a and 2b. (only for pl129j) note: amax = a22 (pl127j), a21 (pl129j and pl064j), a20 (pl032j). logic symbol max+1 16 dq15?dq0 amax?a0 ce# oe# we# reset# ry/by# wp#/acc v io (v ccq )
24 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addres- sable memory location. the register is a latc h used to store the commands, along with the address and data information need ed to execute the command. the contents of the register serve as inputs to the internal state machine. the stat e machine outputs dictate the function of the de- vice. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describ e each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 8.5?9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the high voltage sector protection section. 2. wp#/acc must be high when writin g to upper two and lower two sectors. requirements for reading array data to read array data from the outputs, the syst em must drive the oe# and appropriate ce# pins (for pl129j - ce1#/ce2# pins) to v il . in pl129j, ce1# and ce2# are the power control and se- lect the lower (ce1#) or upper (ce2#) halves of the device. ce# is the power control. oe# is the output control and gates arra y data to the output pins . we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enable d for read access until the command register con- tents are altered. refer to ta b l e 2 8 for timing specifications and to figure 11 for the timing diagram. i cc1 in the dc characteristics table represents the active current specification for reading array data. ta b l e 1 . pl127j device bus operations operation ce# oe# we# reset# wp#/acc addresses (amax?a0) dq15? dq0 read l l h h x a in d out write l h l h x ( note 2 ) a in d in standby v io 0.3 v x x v io 0.3 v x ( note 2 ) x high-z output disable l h h h x x high-z reset x x x l x x high-z temporary sector unprotect (high voltage) x x x v id x a in d in ta b l e 2 . pl129j device bus operations operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21?a0) dq15? dq0 read l h l h h x a in d out h l write l h h l h x ( note 2 ) a in d in h l standby v io 0.3 v v io 0.3 v x x v io 0.3 v x x high-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) x x x x v id x a in d in
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 25 advance information random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addr esses and stable ce# to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid data at the output inputs (assuming the addresses have been stable for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. address bits amax?a3 select an 8 word page, and address bits a2?a0 select a specific word within that page. this is an asynchronous operation wi th the microprocessor supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# (ce1# and ce#2 in pl129j) is deasserted (=v ih ), the reassertion of ce# (ce1# or ce#2 in pl129j) for subsequent access has access time of t acc or t ce . here again, ce# (ce1# /ce#2 in pl129j)selects the device and oe# is the output co ntrol and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping amax? a3 constant and changing a2?a0 to select the specific word within that page. simultaneous read/write operation in addition to the conventional features (read, program, erase-suspend read, erase-suspend pro- gram, and program-suspend read), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simulta- neous operation). the bank can be selected by bank addresses (pl127j: a22?a20, pl129j and pl064j: a21?a19, pl032j: a20?a18) with zero latency. the simultaneous operation can execute multi-function mode in the same bank. ta b l e 3 . page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 ta b l e 0 . 1 bank select bank pl127j: a22?a20 pl064j: a21?a19 pl032j: a20?a18 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111
26 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information writing commands/command sequences to write a command or command sequence (which includes programming da ta to the device and erasing sectors of memory), the system must dr ive we# and ce# (ce1# or ce#2 in pl129j) to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once a bank en- ters the unlock bypass mode, only two write cycl es are required to program a word, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 4 indicates the set of address space that each sector occupi es. a ?bank address? is the set of address bits required to uniquely select a bank. similarly, a ?sec tor address? refers to the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. i cc2 in the dc characteristics table represents the active current specification for the write mode. see the timing specific ation tables and timing diagrams in the reset section for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is pri- marily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatica lly enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle pro- gram command sequence as required by the unlock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated programming , or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is , the wp#/acc pin should not be left floating or unconne cted; inconsistent behavior of the device may result. autoselect functions if the system writes the autoselect command se quence, the device enters the autoselect mode. the system can then read autosele ct codes from the internal regist er (which is separate from the memory array) on dq15?dq0. standard read cy cle timings apply in this mode. refer to the se- cured silicon sector addresses and autoselect command sequence for more information. standby mode when the system is not reading or writing to th e device, it can place the device in the standby mode. in this mode, current consumption is grea tly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# (ce1#,ce#2 in pl129j) and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# (ce1#,ce#2 in pl129j) and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. bank ce1# ce2# pl129j: a21?a20 bank 1a 0 1 00 bank 1b 0 1 01, 10, 11 bank 2a 1 0 00, 01, 10 bank 2b 1 0 11
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 27 advance information i cc3 in dc characteristics represents the cmos standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control si gnals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automatic slee p mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. i cc5 in dc characteristics repre- sents the automatic sleep mo de current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re setting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins , and ignores all read/write commands for the du- ration of the reset# pulse. the device also re sets the internal state machine to reading array data. the operation that was interru pted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or eras e operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristic tables for reset# parameters and to figure 13 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/ by#) are placed in the highest impedance state
28 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ta b l e 4 . pl127j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h?000fffh sa1 00000000001 4 001000h?001fffh sa2 00000000010 4 002000h?002fffh sa3 00000000011 4 003000h?003fffh sa4 00000000100 4 004000h?004fffh sa5 00000000101 4 005000h?005fffh sa6 00000000110 4 006000h?006fffh sa7 00000000111 4 007000h?007fffh sa8 00000001xxx 32 008000h?00ffffh sa9 00000010xxx 32 010000h?017fffh sa10 00000011xxx 32 018000h?01ffffh sa11 00000100xxx 32 020000h?027fffh sa12 00000101xxx 32 028000h?02ffffh sa13 00000110xxx 32 030000h?037fffh sa14 00000111xxx 32 038000h?03ffffh sa15 00001000xxx 32 040000h?047fffh sa16 00001001xxx 32 048000h?04ffffh sa17 00001010xxx 32 050000h?057fffh sa18 00001011xxx 32 058000h?05ffffh sa19 00001100xxx 32 060000h?067fffh sa20 00001101xxx 32 068000h?06ffffh sa21 00001110xxx 32 070000h?077fffh sa22 00001111xxx 32 078000h?07ffffh sa23 00010000xxx 32 080000h?087fffh sa24 00010001xxx 32 088000h?08ffffh sa25 00010010xxx 32 090000h?097fffh sa26 00010011xxx 32 098000h?09ffffh sa27 00010100xxx 32 0a0000h?0a7fffh sa28 00010101xxx 32 0a8000h?0affffh sa29 00010110xxx 32 0b0000h?0b7fffh sa30 00010111xxx 32 0b8000h?0bffffh sa31 00011000xxx 32 0c0000h?0c7fffh sa32 00011001xxx 32 0c8000h?0cffffh sa33 00011010xxx 32 0d0000h?0d7fffh sa34 00011011xxx 32 0d8000h?0dffffh sa35 00011100xxx 32 0e0000h?0e7fffh sa36 00011101xxx 32 0e8000h?0effffh sa37 00011110xxx 32 0f0000h?0f7fffh sa38 00011111xxx 32 0f8000h?0fffffh
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 29 advance information bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h?1d7fffh sa66 00111011xxx 32 1d8000h?1dffffh sa67 00111100xxx 32 1e0000h?1e7fffh sa68 00111101xxx 32 1e8000h?1effffh sa69 00111110xxx 32 1f0000h?1f7fffh sa70 00111111xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
30 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank b sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 01011111xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 31 advance information bank b sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 01111000xxx 32 3c0000h?3c7fffh sa128 01111001xxx 32 3c8000h?3cffffh sa129 01111010xxx 32 3d0000h?3d7fffh sa130 01111011xxx 32 3d8000h?3dffffh sa131 01111100xxx 32 3e0000h?3e7fffh sa132 01111101xxx 32 3e8000h?3effffh sa133 01111110xxx 32 3f0000h?3f7fffh sa134 01111111xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
32 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank c sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh sa164 10011101xxx 32 4e8000h?4effffh sa165 10011110xxx 32 4f0000h?4f7fffh sa166 10011111xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 530000h?537fffh sa174 10100111xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 10111110xxx 32 5f0000h?5f7fffh sa198 10111111xxx 32 5f8000h?5fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 33 advance information bank c sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa207 11001000xxx 32 640000h?647fffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh sa213 11001110xxx 32 670000h?677fffh sa214 11001111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 11011110xxx 32 6f0000h?6f7fffh sa230 11011111xxx 32 6f8000h?6fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
34 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank d sa231 11100000xxx 32 700000h?707fffh sa232 11100001xxx 32 708000h?70ffffh sa233 11100010xxx 32 710000h?717fffh sa234 11100011xxx 32 718000h?71ffffh sa235 11100100xxx 32 720000h?727fffh sa236 11100101xxx 32 728000h?72ffffh sa237 11100110xxx 32 730000h?737fffh sa238 11100111xxx 32 738000h?73ffffh sa239 11101000xxx 32 740000h?747fffh sa240 11101001xxx 32 748000h?74ffffh sa241 11101010xxx 32 750000h?757fffh sa242 11101011xxx 32 758000h?75ffffh sa243 11101100xxx 32 760000h?767fffh sa244 11101101xxx 32 768000h?76ffffh sa245 11101110xxx 32 770000h?777fffh sa246 11101111xxx 32 778000h?77ffffh sa247 11110000xxx 32 780000h?787fffh sa248 11110001xxx 32 788000h?78ffffh sa249 11110010xxx 32 790000h?797fffh sa250 11110011xxx 32 798000h?79ffffh sa251 11110100xxx 32 7a0000h?7a7fffh sa252 11110101xxx 32 7a8000h?7affffh sa253 11110110xxx 32 7b0000h?7b7fffh sa254 11110111xxx 32 7b8000h?7bffffh sa255 11111000xxx 32 7c0000h?7c7fffh sa256 11111001xxx 32 7c8000h?7cffffh sa257 11111010xxx 32 7d0000h?7d7fffh sa258 11111011xxx 32 7d8000h?7dffffh sa259 11111100xxx 32 7e0000h?7e7fffh sa260 11111101xxx 32 7e8000h?7effffh sa261 11111110xxx 32 7f0000h?7f7fffh sa262 11111111000 4 7f8000h?7f8fffh sa263 11111111001 4 7f9000h?7f9fffh sa264 11111111010 4 7fa000h?7fafffh sa265 11111111011 4 7fb000h?7fbfffh sa266 11111111100 4 7fc000h?7fcfffh sa267 11111111101 4 7fd000h?7fdfffh sa268 11111111110 4 7fe000h?7fefffh sa269 11111111111 4 7ff000h?7fffffh table 4. pl127j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 35 advance information ta b l e 5 . pl064j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 0000000000 4 000000h?000fffh sa1 0000000001 4 001000h?001fffh sa2 0000000010 4 002000h?002fffh sa3 0000000011 4 003000h?003fffh sa4 0000000100 4 004000h?004fffh sa5 0000000101 4 005000h?005fffh sa6 0000000110 4 006000h?006fffh sa7 0000000111 4 007000h?007fffh sa8 0000001xxx 32 008000h?00ffffh sa9 0000010xxx 32 010000h?017fffh sa10 0000011xxx 32 018000h?01ffffh sa11 0000100xxx 32 020000h?027fffh sa12 0000101xxx 32 028000h?02ffffh sa13 0000110xxx 32 030000h?037fffh sa14 0000111xxx 32 038000h?03ffffh sa15 0001000xxx 32 040000h?047fffh sa16 0001001xxx 32 048000h?04ffffh sa17 0001010xxx 32 050000h?057fffh sa18 0001011xxx 32 058000h?05ffffh sa19 0001100xxx 32 060000h?067fffh sa20 0001101xxx 32 068000h?06ffffh sa21 0001110xxx 32 070000h?077fffh sa22 0001111xxx 32 078000h?07ffffh bank b sa23 0010000xxx 32 080000h?087fffh sa24 0010001xxx 32 088000h?08ffffh sa25 0010010xxx 32 090000h?097fffh sa26 0010011xxx 32 098000h?09ffffh sa27 0010100xxx 32 0a0000h?0a7fffh sa28 0010101xxx 32 0a8000h?0affffh sa29 0010110xxx 32 0b0000h?0b7fffh sa30 0010111xxx 32 0b8000h?0bffffh sa31 0011000xxx 32 0c0000h?0c7fffh sa32 0011001xxx 32 0c8000h?0cffffh sa33 0011010xxx 32 0d0000h?0d7fffh sa34 0011011xxx 32 0d8000h?0dffffh sa35 0011100xxx 32 0e0000h?0e7fffh sa36 0011101xxx 32 0e8000h?0effffh sa37 0011110xxx 32 0f0000h?0f7fffh sa38 0011111xxx 32 0f8000h?0fffffh sa39 0100000xxx 32 100000h?107fffh sa40 0100001xxx 32 108000h?10ffffh sa41 0100010xxx 32 110000h?117fffh sa42 0100011xxx 32 118000h?11ffffh sa43 0100100xxx 32 120000h?127fffh sa44 0100101xxx 32 128000h?12ffffh sa45 0100110xxx 32 130000h?137fffh sa46 0100111xxx 32 138000h?13ffffh sa47 0101000xxx 32 140000h?147fffh
36 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank b sa48 0101001xxx 32 148000h?14ffffh sa49 0101010xxx 32 150000h?157fffh sa50 0101011xxx 32 158000h?15ffffh sa51 0101100xxx 32 160000h?167fffh sa52 0101101xxx 32 168000h?16ffffh sa53 0101110xxx 32 170000h?177fffh sa54 0101111xxx 32 178000h?17ffffh sa55 0110000xxx 32 180000h?187fffh sa56 0110001xxx 32 188000h?18ffffh sa57 0110010xxx 32 190000h?197fffh sa58 0110011xxx 32 198000h?19ffffh sa59 0110100xxx 32 1a0000h?1a7fffh sa60 0110101xxx 32 1a8000h?1affffh sa61 0110110xxx 32 1b0000h?1b7fffh sa62 0110111xxx 32 1b8000h?1bffffh sa63 0111000xxx 32 1c0000h?1c7fffh sa64 0111001xxx 32 1c8000h?1cffffh sa65 0111010xxx 32 1d0000h?1d7fffh sa66 0111011xxx 32 1d8000h?1dffffh sa67 0111100xxx 32 1e0000h?1e7fffh sa68 0111101xxx 32 1e8000h?1effffh sa69 0111110xxx 32 1f0000h?1f7fffh sa70 0111111xxx 32 1f8000h?1fffffh bank c sa71 1000000xxx 32 200000h?207fffh sa72 1000001xxx 32 208000h?20ffffh sa73 1000010xxx 32 210000h?217fffh sa74 1000011xxx 32 218000h?21ffffh sa75 1000100xxx 32 220000h?227fffh sa76 1000101xxx 32 228000h?22ffffh sa77 1000110xxx 32 230000h?237fffh sa78 1000111xxx 32 238000h?23ffffh sa79 1001000xxx 32 240000h?247fffh sa80 1001001xxx 32 248000h?24ffffh sa81 1001010xxx 32 250000h?257fffh sa82 1001011xxx 32 258000h?25ffffh sa83 1001100xxx 32 260000h?267fffh sa84 1001101xxx 32 268000h?26ffffh sa85 1001110xxx 32 270000h?277fffh sa86 1001111xxx 32 278000h?27ffffh bank c sa87 1010000xxx 32 280000h?287fffh sa88 1010001xxx 32 288000h?28ffffh sa89 1010010xxx 32 290000h?297fffh sa90 1010011xxx 32 298000h?29ffffh sa91 1010100xxx 32 2a0000h?2a7fffh sa92 1010101xxx 32 2a8000h?2affffh sa93 1010110xxx 32 2b0000h?2b7fffh sa94 1010111xxx 32 2b8000h?2bffffh sa95 1011000xxx 32 2c0000h?2c7fffh table 5. pl064j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 37 advance information bank c sa96 1011001xxx 32 2c8000h?2cffffh sa97 1011010xxx 32 2d0000h?2d7fffh sa98 1011011xxx 32 2d8000h?2dffffh sa99 1011100xxx 32 2e0000h?2e7fffh sa100 1011101xxx 32 2e8000h?2effffh sa101 1011110xxx 32 2f0000h?2f7fffh sa102 1011111xxx 32 2f8000h?2fffffh sa103 1100000xxx 32 300000h?307fffh sa104 1100001xxx 32 308000h?30ffffh sa105 1100010xxx 32 310000h?317fffh sa106 1100011xxx 32 318000h?31ffffh sa107 1100100xxx 32 320000h?327fffh sa108 1100101xxx 32 328000h?32ffffh sa109 1100110xxx 32 330000h?337fffh sa110 1100111xxx 32 338000h?33ffffh sa111 1101000xxx 32 340000h?347fffh sa112 1101001xxx 32 348000h?34ffffh sa113 1101010xxx 32 350000h?357fffh sa114 1101011xxx 32 358000h?35ffffh sa115 1101100xxx 32 360000h?367fffh sa116 1101101xxx 32 368000h?36ffffh sa117 1101110xxx 32 370000h?377fffh sa118 1101111xxx 32 378000h?37ffffh bank d sa119 1110000xxx 32 380000h?387fffh sa120 1110001xxx 32 388000h?38ffffh sa121 1110010xxx 32 390000h?397fffh sa122 1110011xxx 32 398000h?39ffffh sa123 1110100xxx 32 3a0000h?3a7fffh sa124 1110101xxx 32 3a8000h?3affffh sa125 1110110xxx 32 3b0000h?3b7fffh sa126 1110111xxx 32 3b8000h?3bffffh sa127 1111000xxx 32 3c0000h?3c7fffh sa128 1111001xxx 32 3c8000h?3cffffh sa129 1111010xxx 32 3d0000h?3d7fffh sa130 1111011xxx 32 3d8000h?3dffffh sa131 1111100xxx 32 3e0000h?3e7fffh sa132 1111101xxx 32 3e8000h?3effffh sa133 1111110xxx 32 3f0000h?3f7fffh sa134 1111111000 4 3f8000h?3f8fffh sa135 1111111001 4 3f9000h?3f9fffh sa136 1111111010 4 3fa000h?3fafffh sa137 1111111011 4 3fb000h?3fbfffh sa138 1111111100 4 3fc000h?3fcfffh sa139 1111111101 4 3fd000h?3fdfffh sa140 1111111110 4 3fe000h?3fefffh sa141 1111111111 4 3ff000h?3fffffh table 5. pl064j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
38 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ta b l e 6 . pl032j sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 000000000 4 000000h?000fffh sa1 000000001 4 001000h?001fffh sa2 000000010 4 002000h?002fffh sa3 000000011 4 003000h?003fffh sa4 000000100 4 004000h?004fffh sa5 000000101 4 005000h?005fffh sa6 000000110 4 006000h?006fffh sa7 000000111 4 007000h?007fffh sa8 000001xxx 32 008000h?00ffffh sa9 000010xxx 32 010000h?017fffh sa10 000011xxx 32 018000h?01ffffh sa11 000100xxx 32 020000h?027fffh sa12 000101xxx 32 028000h?02ffffh sa13 000110xxx 32 030000h?037fffh sa14 000111xxx 32 038000h?03ffffh bank b sa15 001000xxx 32 040000h?047fffh sa16 001001xxx 32 048000h?04ffffh sa17 001010xxx 32 050000h?057fffh sa18 001011xxx 32 058000h?05ffffh sa19 001100xxx 32 060000h?067fffh sa20 001101xxx 32 068000h?06ffffh sa21 001110xxx 32 070000h?077fffh sa22 001111xxx 32 078000h?07ffffh sa23 010000xxx 32 080000h?087fffh sa24 010001xxx 32 088000h?08ffffh sa25 010010xxx 32 090000h?097fffh sa26 010011xxx 32 098000h?09ffffh sa27 010100xxx 32 0a0000h?0a7fffh sa28 010101xxx 32 0a8000h?0affffh sa29 010110xxx 32 0b0000h?0b7fffh sa30 010111xxx 32 0b8000h?0bffffh sa31 011000xxx 32 0c0000h?0c7fffh sa32 011001xxx 32 0c8000h?0cffffh sa33 011010xxx 32 0d0000h?0d7fffh sa34 011011xxx 32 0d8000h?0dffffh sa35 011100xxx 32 0e0000h?0e7fffh sa36 011101xxx 32 0e8000h?0effffh sa37 011110xxx 32 0f0000h?0f7fffh sa38 011111xxx 32 0f8000h?0fffffh
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 39 advance information bank c sa39 100000xxx 32 100000h?107fffh sa40 100001xxx 32 108000h?10ffffh sa41 100010xxx 32 110000h?117fffh sa42 100011xxx 32 118000h?11ffffh sa43 100100xxx 32 120000h?127fffh sa44 100101xxx 32 128000h?12ffffh sa45 100110xxx 32 130000h?137fffh sa46 100111xxx 32 138000h?13ffffh sa47 101000xxx 32 140000h?147fffh sa48 101001xxx 32 148000h?14ffffh sa49 101010xxx 32 150000h?157fffh sa50 101011xxx 32 158000h?15ffffh sa51 101100xxx 32 160000h?167fffh sa52 101101xxx 32 168000h?16ffffh sa53 101110xxx 32 170000h?177fffh sa54 101111xxx 32 178000h?17ffffh sa55 110000xxx 32 180000h?187fffh sa56 110001xxx 32 188000h?18ffffh sa57 110010xxx 32 190000h?197fffh sa58 110011xxx 32 198000h?19ffffh sa59 110100xxx 32 1a0000h?1a7fffh sa60 110101xxx 32 1a8000h?1affffh sa61 110110xxx 32 1b0000h?1b7fffh sa62 110111xxx 32 1b8000h?1bffffh bank d sa63 111000xxx 32 1c0000h?1c7fffh sa64 111001xxx 32 1c8000h?1cffffh sa65 111010xxx 32 1d0000h?1d7fffh sa66 111011xxx 32 1d8000h?1dffffh sa67 111100xxx 32 1e0000h?1e7fffh sa68 111101xxx 32 1e8000h?1effffh sa69 111110xxx 32 1f0000h?1f7fffh sa70 111111000 4 1f8000h?1f8fffh sa71 111111001 4 1f9000h?1f9fffh sa72 111111010 4 1fa000h?1fafffh sa73 111111011 4 1fb000h?1fbfffh sa74 111111100 4 1fc000h?1fcfffh sa75 111111101 4 1fd000h?1fdfffh sa76 111111110 4 1fe000h?1fefffh sa77 111111111 4 1ff000h?1fffffh table 6. pl032j sector architecture (continued) bank sector sector address (a22-a12) sector size (kwords) address range (x16)
40 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ta b l e 7 . s29pl129j sector architecture bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16) bank 1a sa1-0 0 1 0000000000 4 000000h?000fffh sa1-1 0 1 0000000001 4 001000h?001fffh sa1-2 0 1 0000000010 4 002000h?002fffh sa1-3 0 1 0000000011 4 003000h?003fffh sa1-4 0 1 0000000100 4 004000h?004fffh sa1-5 0 1 0000000101 4 005000h?005fffh sa1-6 0 1 0000000110 4 006000h?006fffh sa1-7 0 1 0000000111 4 007000h?007fffh sa1-8 0 1 0000001xxx 32 008000h?00ffffh sa1-9 0 1 0000010xxx 32 010000h?017fffh sa1-10 0 1 0000011xxx 32 018000h?01ffffh sa1-11 0 1 0000100xxx 32 020000h?027fffh sa1-12 0 1 0000101xxx 32 028000h?02ffffh sa1-13 0 1 0000110xxx 32 030000h?037fffh sa1-14 0 1 0000111xxx 32 038000h?03ffffh sa1-15 0 1 0001000xxx 32 040000h?047fffh sa1-16 0 1 0001001xxx 32 048000h?04ffffh sa1-17 0 1 0001010xxx 32 050000h?057fffh sa1-18 0 1 0001011xxx 32 058000h?05ffffh sa1-19 0 1 0001100xxx 32 060000h?067fffh sa1-20 0 1 0001101xxx 32 068000h?06ffffh sa1-21 0 1 0001110xxx 32 070000h?077fffh sa1-22 0 1 0001111xxx 32 078000h?07ffffh sa1-23 0 1 0010000xxx 32 080000h?087fffh sa1-24 0 1 0010001xxx 32 088000h?08ffffh sa1-25 0 1 0010010xxx 32 090000h?097fffh sa1-26 0 1 0010011xxx 32 098000h?09ffffh sa1-27 0 1 0010100xxx 32 0a0000h?0a7fffh sa1-28 0 1 0010101xxx 32 0a8000h?0affffh sa1-29 0 1 0010110xxx 32 0b0000h?0b7fffh sa1-30 0 1 0010111xxx 32 0b8000h?0bffffh sa1-31 0 1 0011000xxx 32 0c0000h?0c7fffh sa1-32 0 1 0011001xxx 32 0c8000h?0cffffh sa1-33 0 1 0011010xxx 32 0d0000h?0d7fffh sa1-34 0 1 0011011xxx 32 0d8000h?0dffffh sa1-35 0 1 0011100xxx 32 0e0000h?0e7fffh sa1-36 0 1 0011101xxx 32 0e8000h?0effffh sa1-37 0 1 0011110xxx 32 0f0000h?0f7fffh sa1-38 0 1 0011111xxx 32 0f8000h?0fffffh
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 41 advance information bank 1b sa1-39 0 1 0100000xxx 32 100000h?107fffh sa1-40 0 1 0100001xxx 32 108000h?10ffffh sa1-41 0 1 0100010xxx 32 110000h?117fffh sa1-42 0 1 0100011xxx 32 118000h?11ffffh sa1-43 0 1 0100100xxx 32 120000h?127fffh sa1-44 0 1 0100101xxx 32 128000h?12ffffh sa1-45 0 1 0100110xxx 32 130000h?137fffh sa1-46 0 1 0100111xxx 32 138000h?13ffffh sa1-47 0 1 0101000xxx 32 140000h?147fffh sa1-48 0 1 0101001xxx 32 148000h?14ffffh sa1-49 0 1 0101010xxx 32 150000h?157fffh sa1-50 0 1 0101011xxx 32 158000h?15ffffh sa1-51 0 1 0101100xxx 32 160000h?167fffh sa1-52 0 1 0101101xxx 32 168000h?16ffffh sa1-53 0 1 0101110xxx 32 170000h?177fffh sa1-54 0 1 0101111xxx 32 178000h?17ffffh sa1-55 0 1 0110000xxx 32 180000h?187fffh sa1-56 0 1 0110001xxx 32 188000h?18ffffh sa1-57 0 1 0110010xxx 32 190000h?197fffh sa1-58 0 1 0110011xxx 32 198000h?19ffffh sa1-59 0 1 0110100xxx 32 1a0000h?1a7fffh sa1-60 0 1 0110101xxx 32 1a8000h?1affffh sa1-61 0 1 0110110xxx 32 1b0000h?1b7fffh sa1-62 0 1 0110111xxx 32 1b8000h?1bffffh sa1-63 0 1 0111000xxx 32 1c0000h?1c7fffh sa1-64 0 1 0111001xxx 32 1c8000h?1cffffh sa1-65 0 1 0111010xxx 32 1d0000h?1d7fffh sa1-66 0 1 0111011xxx 32 1d8000h?1dffffh sa1-67 0 1 0111100xxx 32 1e0000h?1e7fffh sa1-68 0 1 0111101xxx 32 1e8000h?1effffh sa1-69 0 1 0111110xxx 32 1f0000h?1f7fffh sa1-70 0 1 0111111xxx 32 1f8000h?1fffffh sa1-71 0 1 1000000xxx 32 200000h?207fffh sa1-72 0 1 1000001xxx 32 208000h?20ffffh sa1-73 0 1 1000010xxx 32 210000h?217fffh sa1-74 0 1 1000011xxx 32 218000h?21ffffh sa1-75 0 1 1000100xxx 32 220000h?227fffh sa1-76 0 1 1000101xxx 32 228000h?22ffffh sa1-77 0 1 1000110xxx 32 230000h?237fffh sa1-78 0 1 1000111xxx 32 238000h?23ffffh sa1-79 0 1 1001000xxx 32 240000h?247fffh sa1-80 0 1 1001001xxx 32 248000h?24ffffh sa1-81 0 1 1001010xxx 32 250000h?257fffh sa1-82 0 1 1001011xxx 32 258000h?25ffffh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
42 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank 1b sa1-83 0 1 1001100xxx 32 260000h?267fffh sa1-84 0 1 1001101xxx 32 268000h?26ffffh sa1-85 0 1 1001110xxx 32 270000h?277fffh sa1-86 0 1 1001111xxx 32 278000h?27ffffh sa1-87 0 1 1010000xxx 32 280000h?287fffh sa1-88 0 1 1010001xxx 32 288000h?28ffffh sa1-89 0 1 1010010xxx 32 290000h?297fffh sa1-90 0 1 1010011xxx 32 298000h?29ffffh sa1-91 0 1 1010100xxx 32 2a0000h?2a7fffh sa1-92 0 1 1010101xxx 32 2a8000h?2affffh sa1-93 0 1 1010110xxx 32 2b0000h?2b7fffh sa1-94 0 1 1010111xxx 32 2b8000h?2bffffh sa1-95 0 1 1011000xxx 32 2c0000h?2c7fffh sa1-96 0 1 1011001xxx 32 2c8000h?2cffffh sa1-97 0 1 1011010xxx 32 2d0000h?2d7fffh sa1-98 0 1 1011011xxx 32 2d8000h?2dffffh sa1-99 0 1 1011100xxx 32 2e0000h?2e7fffh sa1-100 0 1 1011101xxx 32 2e8000h?2effffh sa1-101 0 1 1011110xxx 32 2f0000h?2f7fffh sa1-102 0 1 1011111xxx 32 2f8000h?2fffffh sa1-103 0 1 1100000xxx 32 300000h?307fffh sa1-104 0 1 1100001xxx 32 308000h?30ffffh sa1-105 0 1 1100010xxx 32 310000h?317fffh sa1-106 0 1 1100011xxx 32 318000h?31ffffh sa1-107 0 1 1100100xxx 32 320000h?327fffh sa1-108 0 1 1100101xxx 32 328000h?32ffffh sa1-109 0 1 1100110xxx 32 330000h?337fffh sa1-110 0 1 1100111xxx 32 338000h?33ffffh sa1-111 0 1 1101000xxx 32 340000h?347fffh sa1-112 0 1 1101001xxx 32 348000h?34ffffh sa1-113 0 1 1101010xxx 32 350000h?357fffh sa1-114 0 1 1101011xxx 32 358000h?35ffffh sa1-115 0 1 1101100xxx 32 360000h?367fffh sa1-116 0 1 1101101xxx 32 368000h?36ffffh sa1-117 0 1 1101110xxx 32 370000h?377fffh sa1-118 0 1 1101111xxx 32 378000h?37ffffh sa1-119 0 1 1110000xxx 32 380000h?387fffh sa1-120 0 1 1110001xxx 32 388000h?38ffffh sa1-121 0 1 1110010xxx 32 390000h?397fffh sa1-122 0 1 1110011xxx 32 398000h?39ffffh sa1-123 0 1 1110100xxx 32 3a0000h?3a7fffh sa1-124 0 1 1110101xxx 32 3a8000h?3affffh sa1-125 0 1 1110110xxx 32 3b0000h?3b7fffh sa1-126 0 1 1110111xxx 32 3b8000h?3bffffh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 43 advance information bank 1b sa1-127 0 1 1111000xxx 32 3c0000h?3c7fffh sa1-128 0 1 1111001xxx 32 3c8000h?3cffffh sa1-129 0 1 1111010xxx 32 3d0000h?3d7fffh sa1-130 0 1 1111011xxx 32 3d8000h?3dffffh sa1-131 0 1 1111100xxx 32 3e0000h?3e7fffh sa1-132 0 1 1111101xxx 32 3e8000h?3effffh sa1-133 0 1 1111110xxx 32 3f0000h?3f7fffh sa1-134 0 1 1111111xxx 32 3f8000h?3fffffh bank 2a sa2-0 1 0 0000000xxx 32 000000h?007fffh sa2-1 1 0 0000001xxx 32 008000h?00ffffh sa2-2 1 0 0000010xxx 32 010000h?017fffh sa2-3 1 0 0000011xxx 32 018000h?01ffffh sa2-4 1 0 0000100xxx 32 020000h?027fffh sa2-5 1 0 0000101xxx 32 028000h?02ffffh sa2-6 1 0 0000110xxx 32 030000h?037fffh sa2-7 1 0 0000111xxx 32 038000h?03ffffh sa2-8 1 0 0001000xxx 32 040000h?047fffh sa2-9 1 0 0001001xxx 32 048000h?04ffffh sa2-10 1 0 0001010xxx 32 050000h?057fffh sa2-11 1 0 0001011xxx 32 058000h?05ffffh sa2-12 1 0 0001100xxx 32 060000h?067fffh sa2-13 1 0 0001101xxx 32 068000h?06ffffh sa2-14 1 0 0001110xxx 32 070000h?077fffh sa2-15 1 0 0001111xxx 32 078000h?07ffffh sa2-16 1 0 0010000xxx 32 080000h?087fffh sa2-17 1 0 0010001xxx 32 088000h?08ffffh sa2-18 1 0 0010010xxx 32 090000h?097fffh sa2-19 1 0 0010011xxx 32 098000h?09ffffh sa2-20 1 0 0010100xxx 32 0a0000h?0a7fffh sa2-21 1 0 0010101xxx 32 0a8000h?0affffh sa2-22 1 0 0010110xxx 32 0b0000h?0b7fffh sa2-23 1 0 0010111xxx 32 0b8000h?0bffffh sa2-24 1 0 0011000xxx 32 0c0000h?0c7fffh sa2-25 1 0 0011001xxx 32 0c8000h?0cffffh sa2-26 1 0 0011010xxx 32 0d0000h?0d7fffh sa2-27 1 0 0011011xxx 32 0d8000h?0dffffh sa2-28 1 0 0011100xxx 32 0e0000h?0e7fffh sa2-29 1 0 0011101xxx 32 0e8000h?0effffh sa2-30 1 0 0011110xxx 32 0f0000h?0f7fffh sa2-31 1 0 0011111xxx 32 0f8000h?0fffffh sa2-32 1 0 0100000xxx 32 100000h?107fffh sa2-33 1 0 0100001xxx 32 108000h?10ffffh sa2-34 1 0 0100010xxx 32 110000h?117fffh sa2-35 1 0 0100011xxx 32 118000h?11ffffh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
44 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information bank 2a sa2-36 1 0 0100100xxx 32 120000h?127fffh sa2-37 1 0 0100101xxx 32 128000h?12ffffh sa2-38 1 0 0100110xxx 32 130000h?137fffh sa2-39 1 0 0100111xxx 32 138000h?13ffffh sa2-40 1 0 0101000xxx 32 140000h?147fffh sa2-41 1 0 0101001xxx 32 148000h?14ffffh sa2-42 1 0 0101010xxx 32 150000h?157fffh sa2-43 1 0 0101011xxx 32 158000h?15ffffh bank 2a sa2-44 1 0 0101100xxx 32 160000h?167fffh sa2-45 1 0 0101101xxx 32 168000h?16ffffh sa2-46 1 0 0101110xxx 32 170000h?177fffh sa2-47 1 0 0101111xxx 32 178000h?17ffffh sa2-48 1 0 0110000xxx 32 180000h?187fffh sa2-49 1 0 0110001xxx 32 188000h?18ffffh sa2-50 1 0 0110010xxx 32 190000h?197fffh sa2-51 1 0 0110011xxx 32 198000h?19ffffh sa2-52 1 0 0110100xxx 32 1a0000h?1a7fffh sa2-53 1 0 0110101xxx 32 1a8000h?1affffh sa2-54 1 0 0110110xxx 32 1b0000h?1b7fffh sa2-55 1 0 0110111xxx 32 1b8000h?1bffffh sa2-56 1 0 0111000xxx 32 1c0000h?1c7fffh sa2-57 1 0 0111001xxx 32 1c8000h?1cffffh sa2-58 1 0 0111010xxx 32 1d0000h?1d7fffh sa2-59 1 0 0111011xxx 32 1d8000h?1dffffh sa2-60 1 0 0111100xxx 32 1e0000h?1e7fffh sa2-61 1 0 0111101xxx 32 1e8000h?1effffh sa2-62 1 0 0111110xxx 32 1f0000h?1f7fffh sa2-63 1 0 0111111xxx 32 1f8000h?1fffffh sa2-64 1 0 1000000xxx 32 200000h?207fffh sa2-65 1 0 1000001xxx 32 208000h?20ffffh sa2-66 1 0 1000010xxx 32 210000h?217fffh sa2-67 1 0 1000011xxx 32 218000h?21ffffh sa2-68 1 0 1000100xxx 32 220000h?227fffh sa2-69 1 0 1000101xxx 32 228000h?22ffffh sa2-70 1 0 1000110xxx 32 230000h?237fffh sa2-71 1 0 1000111xxx 32 238000h?23ffffh sa2-72 1 0 1001000xxx 32 240000h?247fffh sa2-73 1 0 1001001xxx 32 248000h?24ffffh sa2-74 1 0 1001010xxx 32 250000h?257fffh sa2-75 1 0 1001011xxx 32 258000h?25ffffh sa2-76 1 0 1001100xxx 32 260000h?267fffh sa2-77 1 0 1001101xxx 32 268000h?26ffffh sa2-78 1 0 1001110xxx 32 270000h?277fffh sa2-79 1 0 1001111xxx 32 278000h?27ffffh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 45 advance information bank 2a sa2-80 1 0 1010000xxx 32 280000h?287fffh sa2-81 1 0 1010001xxx 32 288000h?28ffffh sa2-82 1 0 1010010xxx 32 290000h?297fffh sa2-83 1 0 1010011xxx 32 298000h?29ffffh sa2-84 1 0 1010100xxx 32 2a0000h?2a7fffh sa2-85 1 0 1010101xxx 32 2a8000h?2affffh sa2-86 1 0 1010110xxx 32 2b0000h?2b7fffh sa2-87 1 0 1010111xxx 32 2b8000h?2bffffh sa2-88 1 0 1011000xxx 32 2c0000h?2c7fffh sa2-89 1 0 1011001xxx 32 2c8000h?2cffffh sa2-90 1 0 1011010xxx 32 2d0000h?2d7fffh sa2-91 1 0 1011011xxx 32 2d8000h?2dffffh sa2-92 1 0 1011100xxx 32 2e0000h?2e7fffh sa2-93 1 0 1011101xxx 32 2e8000h?2effffh sa2-94 1 0 1011110xxx 32 2f0000h?2f7fffh sa2-95 1 0 1011111xxx 32 2f8000h?2fffffh bank 2b sa2-96 1 0 1100000xxx 32 300000h?307fffh sa2-97 1 0 1100001xxx 32 308000h?30ffffh sa2-98 1 0 1100010xxx 32 310000h?317fffh sa2-99 1 0 1100011xxx 32 318000h?31ffffh sa2-100 1 0 1100100xxx 32 320000h?327fffh sa2-101 1 0 1100101xxx 32 328000h?32ffffh sa2-102 1 0 1100110xxx 32 330000h?337fffh sa2-103 1 0 1100111xxx 32 338000h?33ffffh sa2-104 1 0 1101000xxx 32 340000h?347fffh sa2-105 1 0 1101001xxx 32 348000h?34ffffh sa2-106 1 0 1101010xxx 32 350000h?357fffh sa2-107 1 0 1101011xxx 32 358000h?35ffffh sa2-108 1 0 1101100xxx 32 360000h?367fffh sa2-109 1 0 1101101xxx 32 368000h?36ffffh sa2-110 1 0 1101110xxx 32 370000h?377fffh sa2-111 1 0 1101111xxx 32 378000h?37ffffh sa2-112 1 0 1110000xxx 32 380000h?387fffh sa2-113 1 0 1110001xxx 32 388000h?38ffffh sa2-114 1 0 1110010xxx 32 390000h?397fffh sa2-115 1 0 1110011xxx 32 398000h?39ffffh sa2-116 1 0 1110100xxx 32 3a0000h?3a7fffh sa2-117 1 0 1110101xxx 32 3a8000h?3affffh sa2-118 1 0 1110110xxx 32 3b0000h?3b7fffh sa2-119 1 0 1110111xxx 32 3b8000h?3bffffh sa2-120 1 0 1111000xxx 32 3c0000h?3c7fffh sa2-121 1 0 1111001xxx 32 3c8000h?3cffffh sa2-122 1 0 1111010xxx 32 3d0000h?3d7fffh sa2-123 1 0 1111011xxx 32 3d8000h?3dffffh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
46 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information autoselect mode the autoselect mode provides manufacturer and de vice identification, and sector protection ver- ification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automa tically match a device to be programmed with its correspond- ing programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. ad- dress pins must be as shown in ta b l e 9 and ta b l e 1 0 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see ta b l e 0 . 1 ). ta b l e 9 and ta b l e 1 0 show the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corre- sponding identifier code on dq7?dq0. however, the autoselect codes can also be accessed in- system through the command regi ster, for instances when the device is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in ta b l e 0 . 3 . note that if a bank address (ba) (on address bits pl127j: a22 ? a20, pl129j and pl064j: a21 ? a19, pl032j: a20 ?a18) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank an d then immediately read array data from the other bank, withou t exiting the autoselect mode. to access the autoselect codes in-system, the ho st system can issue the autoselect command via the command register, as shown in ta b l e 0 . 3 . this method does not require v id . refer to the au- toselect command sequence for more information. bank 2b sa2-124 1 0 1111100xxx 32 3e0000h?3e7fffh sa2-125 1 0 1111101xxx 32 3e8000h?3effffh sa2-126 1 0 1111110xxx 32 3f0000h?3f7fffh sa2-127 1 0 1111111000 4 3f8000h?3f8fffh sa2-128 1 0 1111111001 4 3f9000h?3f9fffh sa2-129 1 0 1111111010 4 3fa000h?3fafffh sa2-130 1 0 1111111011 4 3fb000h?3fbfffh sa2-131 1 0 1111111100 4 3fc000h?3fcfffh sa2-132 1 0 1111111101 4 3fd000h?3fdfffh sa2-133 1 0 1111111110 4 3fe000h?3fefffh sa2-134 1 0 1111111111 4 3ff000h?3fffffh ta b l e 8 . secured silicon sector addresses sector size address range factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh table 7. s29pl129j sector architecture (continued) bank sector ce1# ce2# sector address (a21-a12) sector size (kwords) address range (x16)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 47 advance information legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences ta b l e 9 . autoselect codes (high voltage method) description ce# oe# we# amax to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products l l h ba x v i d x l l x l l l l 0001h device id read cycle 1 l l h ba x v i d x l l l l l l h 227eh read cycle 2 l h h h l 2220h (pl127j) 2202h (pl064j) 220ah (pl032j) read cycle 3 l h h h h 2200h (pl127j) 2201h (pl064j) 2201h (pl032j) sector protection verification l l h sa x v i d x l l l l l h l 0001h (protected), 0000h (unprotected) secure sector secured silicon indicator bit (dq7, dq6) l l h ba x v i d x x l x l l h h dq7=1 (factory locked), dq6=1 (factory and customer locked) ta b l e 1 0 . autoselect codes for pl129j description ce1# ce2# oe# we# a21 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products l h l h x x v i d x l l x l l l l 0001h h l device id read cycle 1 l h l h x x v i d x l l l l l l h 227eh h l read cycle 2 l h h h h l 2221h h l read cycle 3 l h h h h h 2200h h l sector protection verification l h l h sa x v i d x l l l l l h l 0001h (protected), 0000h (unprotected) h l secure sector secured silicon indicator bit (dq7, dq6) l h l h x x v i d x x l x l l h h dq7=1 (factory locked), dq6=1 (factory and customer locked) h l
48 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ta b l e 0 . 2 . pl127j boot sector/sector block ad dresses for protection/unprotection sector a22-a12 sector/ sector block size sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa131-sa134 011111xxxxx 128 (4x32) kwords sa1 00000000001 4 kwords sa135-sa138 100000xxxxx 128 (4x32) kwords sa2 00000000010 4 kwords sa139-sa142 100001xxxxx 128 (4x32) kwords sa3 00000000011 4 kwords sa143-sa146 100010xxxxx 128 (4x32) kwords sa4 00000000100 4 kwords sa147-sa150 100011xxxxx 128 (4x32) kwords sa5 00000000101 4 kwords sa151-sa154 100100xxxxx 128 (4x32) kwords sa6 00000000110 4 kwords sa155-sa158 100101xxxxx 128 (4x32) kwords sa7 00000000111 4 kwords sa159-sa162 100110xxxxx 128 (4x32) kwords sa8 00000001xxx 32 kwords sa163-sa166 100111xxxxx 128 (4x32) kwords sa9 00000010xxx 32 kwords sa167-sa170 101000xxxxx 128 (4x32) kwords sa10 00000011xxx 32 kwords sa171-sa174 101001xxxxx 128 (4x32) kwords sa11-sa14 000001xxxxx 128 (4x32) kwords sa175-sa178 101010xxxxx 128 (4x32) kwords sa15-sa18 000010xxxxx 128 (4x32) kwords sa179-sa182 101011xxxxx 128 (4x32) kwords sa19-sa22 000011xxxxx 128 (4x32) kwords sa183-sa186 101100xxxxx 128 (4x32) kwords sa23-sa26 000100xxxxx 128 (4x32) kwords sa187-sa190 101101xxxxx 128 (4x32) kwords sa27-sa30 000101xxxxx 128 (4x32) kwords sa191-sa194 101110xxxxx 128 (4x32) kwords sa31-sa34 000110xxxxx 128 (4x32) kwords sa195-sa198 101111xxxxx 128 (4x32) kwords sa35-sa38 000111xxxxx 128 (4x32) kwords sa199-sa202 110000xxxxx 128 (4x32) kwords sa39-sa42 001000xxxxx 128 (4x32) kwords sa203-sa206 110001xxxxx 128 (4x32) kwords sa43-sa46 001001xxxxx 128 (4x32) kwords sa207-sa210 110010xxxxx 128 (4x32) kwords sa47-sa50 001010xxxxx 128 (4x32) kwords sa211-sa214 110011xxxxx 128 (4x32) kwords sa51-sa54 001011xxxxx 128 (4x32) kwords sa215-sa218 110100xxxxx 128 (4x32) kwords sa55-sa58 001100xxxxx 128 (4x32) kwords sa219-sa222 110101xxxxx 128 (4x32) kwords sa59-sa62 001101xxxxx 128 (4x32) kwords sa223-sa226 110110xxxxx 128 (4x32) kwords sa63-sa66 001110xxxxx 128 (4x32) kwords sa227-sa230 110111xxxxx 128 (4x32) kwords sa67-sa70 001111xxxxx 128 (4x32) kwords sa231-sa234 111000xxxxx 128 (4x32) kwords sa71-sa74 010000xxxxx 128 (4x32) kwords sa235-sa238 111001xxxxx 128 (4x32) kwords sa75-sa78 010001xxxxx 128 (4x32) kwords sa239-sa242 111010xxxxx 128 (4x32) kwords sa79-sa82 010010xxxxx 128 (4x32) kwords sa243-sa246 111011xxxxx 128 (4x32) kwords sa83-sa86 010011xxxxx 128 (4x32) kwords sa247-sa250 111100xxxxx 128 (4x32) kwords sa87-sa90 010100xxxxx 128 (4x32) kwords sa251-sa254 111101xxxxx 128 (4x32) kwords sa91-sa94 010101xxxxx 128 (4x32) kwords sa255-sa258 111110xxxxx 128 (4x32) kwords sa95-sa98 010110xxxxx 128 (4x32) kwords sa259 11111100xxx 32 kwords sa99-sa102 010111xxxxx 128 (4x32) kwords sa260 11111101xxx 32 kwords sa103-sa106 011000xxxxx 128 (4x32) kwords sa261 11111110xxx 32 kwords sa107-sa110 011001xxxxx 128 (4x32) kwords sa262 11111111000 4 kwords sa111-sa114 011010xxxxx 128 (4x32) kwords sa263 11111111001 4 kwords sa115-sa118 011011xxxxx 128 (4x32) kwords sa264 11111111010 4 kwords sa119-sa122 011100xxxxx 128 (4x32) kwords sa265 11111111011 4 kwords sa123-sa126 011101xxxxx 128 (4x32) kwords sa127-sa130 011110xxxxx 128 (4x32) kwords
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 49 advance information ta b l e 1 1 . pl129j boot sector/sector block ad dresses for protection/unprotection ce1# control ce2# control sector group a21-12 sector/sector block size sector group a21-12 sector/sector block size sa1-0 0000000000 4 kwords sa2-0?sa2-3 00000xxxxx 128 (4x32) kwords sa1-1 0000000001 4 kwords sa2-4?sa2-7 00001xxxxx 128 (4x32) kwords sa1-2 0000000010 4 kwords sa2-8?sa2-11 00010xxxxx 128 (4x32) kwords sa1-3 0000000011 4 kwords sa2-12?sa2-15 00011xxxxx 128 (4x32) kwords sa1-4 0000000100 4 kwords sa2-16?sa2-19 00100xxxxx 128 (4x32) kwords sa1-5 0000000101 4 kwords sa2-20?sa2-23 00101xxxxx 128 (4x32) kwords sa1-6 0000000110 4 kwords sa2-24?sa2-27 00110xxxxx 128 (4x32) kwords sa1-7 0000000111 4 kwords sa2-28?sa2-31 00111xxxxx 128 (4x32) kwords sa1-8 0000001xxx 32 kwords sa2-32?sa2-35 01000xxxxx 128 (4x32) kwords sa1-9 0000010xxx 32 kwords sa2-36?sa2-39 01001xxxxx 128 (4x32) kwords sa1-10 0000011xxx 32 kwords sa2-40?sa2-43 01010xxxxx 128 (4x32) kwords sa1-11 - sa1-14 00001xxxxx 128 (4x32) kwords sa2-44?sa2-47 01011xxxxx 128 (4x32) kwords sa1-15 - sa1-18 00010xxxxx 128 (4x32) kwords sa2-48?sa2-51 01100xxxxx 128 (4x32) kwords sa1-19 - sa1-22 00011xxxxx 128 (4x32) kwords sa2-52?sa2-55 01101xxxxx 128 (4x32) kwords sa1-23 - sa1-26 00100xxxxx 128 (4x32) kwords sa2-56?sa2-59 01110xxxxx 128 (4x32) kwords sa1-27 - sa1-30 00101xxxxx 128 (4x32) kwords sa2-60?sa2-63 01111xxxxx 128 (4x32) kwords sa1-31 - sa1-34 00110xxxxx 128 (4x32) kwords sa2-64?sa2-67 10000xxxxx 128 (4x32) kwords sa1-35 - sa1-38 00111xxxxx 128 (4x32) kwords sa2-68?sa2-71 10001xxxxx 128 (4x32) kwords sa1-39 - sa1-42 01000xxxxx 128 (4x32) kwords sa2-72?sa2-75 10010xxxxx 128 (4x32) kwords sa1-43 - sa1-46 01001xxxxx 128 (4x32) kwords sa2-76?sa2-79 10011xxxxx 128 (4x32) kwords sa1-47 - sa1-50 01010xxxxx 128 (4x32) kwords sa2-80?sa2-83 10100xxxxx 128 (4x32) kwords sa1-51 - sa1-54 01011xxxxx 128 (4x32) kwords sa2-84?sa2-87 10101xxxxx 128 (4x32) kwords sa1-55 - sa1-58 01100xxxxx 128 (4x32) kwords sa2-88?sa2-91 10110xxxxx 128 (4x32) kwords sa1-59 - sa1-62 01101xxxxx 128 (4x32) kwords sa2-92?sa2-95 10111xxxxx 128 (4x32) kwords sa1-63 - sa1-66 01110xxxxx 128 (4x32) kwords sa2-96?sa2-99 11000xxxxx 128 (4x32) kwords sa1-67 - sa1-70 01111xxxxx 128 (4x32) kwords sa2-100?sa2-103 11001xxxxx 128 (4x32) kwords sa1-71 - sa1-74 10000xxxxx 128 (4x32) kwords sa2-104?sa2-107 11010xxxxx 128 (4x32) kwords sa1-75 - sa1-78 10001xxxxx 128 (4x32) kwords sa2-108?sa2-111 11011xxxxx 128 (4x32) kwords sa1-79 - sa1-82 10010xxxxx 128 (4x32) kwords sa2-112?sa2-115 11100xxxxx 128 (4x32) kwords sa1-83 - sa1-86 10011xxxxx 128 (4x32) kwords sa2-116?sa2-119 11101xxxxx 128 (4x32) kwords sa1-87 - sa1-90 10100xxxxx 128 (4x32) kwords sa2-120?sa2-123 11110xxxxx 128 (4x32) kwords sa1-91 - sa1-94 10101xxxxx 128 (4x32) kwords sa2-124 1111100xxx 32 kwords sa1-95 - sa1-98 10110xxxxx 128 (4x32) kwords sa2-125 1111101xxx 32 kwords sa1-99 - sa1-102 10111xxxxx 128 (4x32) kwords sa2-126 1111110xxx 32 kwords sa1-103 - sa1- 106 11000xxxxx 128 (4x32) kwords sa2-127 1111111000 4 kwords sa1-107 - sa1- 110 11001xxxxx 128 (4x32) kwords sa2-128 1111111001 4 kwords sa1-111 - sa1- 114 11010xxxxx 128 (4x32) kwords sa2-129 1111111010 4 kwords sa1-115 - sa1- 118 11011xxxxx 128 (4x32) kwords sa2-130 1111111011 4 kwords sa1-119 - sa1- 122 11100xxxxx 128 (4x32) kwords sa2-131 1111111100 4 kwords sa1-123 - sa1- 126 11101xxxxx 128 (4x32) kwords sa2-132 1111111101 4 kwords sa1-127 - sa1- 130 11110xxxxx 128 (4x32) kwords sa2-133 1111111110 4 kwords sa1-131 - sa1- 134 11111xxxxx 128 (4x32) kwords sa2-134 1111111111 4 kwords
50 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ta b l e 1 2 . pl064j boot sector/sector block ad dresses for protection/unprotection sector a21-a12 sector/sector block size sa0 0000000000 4 kwords sa1 0000000001 4 kwords sa2 0000000010 4 kwords sa3 0000000011 4 kwords sa4 0000000100 4 kwords sa5 0000000101 4 kwords sa6 0000000110 4 kwords sa7 0000000111 4 kwords sa8 0000001xxx 32 kwords sa9 0000010xxx 32 kwords sa10 0000011xxx 32 kwords sa11-sa14 00001xxxxx 128 (4x32) kwords sa15-sa18 00010xxxxx 128 (4x32) kwords sa19-sa22 00011xxxxx 128 (4x32) kwords sa23-sa26 00100xxxxx 128 (4x32) kwords sa27-sa30 00101xxxxx 128 (4x32) kwords sa31-sa34 00110xxxxx 128 (4x32) kwords sa35-sa38 00111xxxxx 128 (4x32) kwords sa39-sa42 01000xxxxx 128 (4x32) kwords sa43-sa46 01001xxxxx 128 (4x32) kwords sa47-sa50 01010xxxxx 128 (4x32) kwords sa51-sa54 01011xxxxx 128 (4x32) kwords sa55-sa58 01100xxxxx 128 (4x32) kwords sa59-sa62 01101xxxxx 128 (4x32) kwords sa63-sa66 01110xxxxx 128 (4x32) kwords sa67-sa70 01111xxxxx 128 (4x32) kwords sa71-sa74 10000xxxxx 128 (4x32) kwords sa75-sa78 10001xxxxx 128 (4x32) kwords sa79-sa82 10010xxxxx 128 (4x32) kwords sa83-sa86 10011xxxxx 128 (4x32) kwords sa87-sa90 10100xxxxx 128 (4x32) kwords sa91-sa94 10101xxxxx 128 (4x32) kwords sa95-sa98 10110xxxxx 128 (4x32) kwords sa99-sa102 10111xxxxx 128 (4x32) kwords sa103-sa106 11000xxxxx 128 (4x32) kwords sa107-sa110 11001xxxxx 128 (4x32) kwords sa111-sa114 11010xxxxx 128 (4x32) kwords sa115-sa118 11011xxxxx 128 (4x32) kwords sa119-sa122 11100xxxxx 128 (4x32) kwords sa123-sa126 11101xxxxx 128 (4x32) kwords sa127-sa130 11110xxxxx 128 (4x32) kwords sa131 1111100xxx 32 kwords sa132 1111101xxx 32 kwords sa133 1111110xxx 32 kwords sa134 1111111000 4 kwords sa135 1111111001 4 kwords sa136 1111111010 4 kwords sa137 1111111011 4 kwords sa138 1111111100 4 kwords sa139 1111111101 4 kwords sa140 1111111110 4 kwords sa141 1111111111 4 kwords
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 51 advance information selecting a sector protection mode the device is shipped with all sectors unprotect ed. optional spansion programming services en- able programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sect or is protected or unprotected. see the secured silicon sector addresses for details. ta b l e 1 3 . pl032j boot sector/sector block addresses for protection/unprotection sector a21-a12 sector/sector block size sa0 000000000 4 kwords sa1 000000001 4 kwords sa2 000000010 4 kwords sa3 000000011 4 kwords sa4 000000100 4 kwords sa5 000000101 4 kwords sa6 000000110 4 kwords sa7 000000111 4 kwords sa8 000001xxx 32 kwords sa9 000010xxx 32 kwords sa10 000011xxx 32 kwords sa11-sa14 0001xxxxx 128 (4x32) kwords sa15-sa18 0010xxxxx 128 (4x32) kwords sa19-sa22 0011xxxxx 128 (4x32) kwords sa23-sa26 0100xxxxx 128 (4x32) kwords sa27-sa30 0101xxxxx 128 (4x32) kwords sa31-sa34 0110xxxxx 128 (4x32) kwords sa35-sa38 0111xxxxx 128 (4x32) kwords sa39-sa42 1000xxxxx 128 (4x32) kwords sa43-sa46 1001xxxxx 128 (4x32) kwords sa47-sa50 1010xxxxx 128 (4x32) kwords sa51-sa54 1011xxxxx 128 (4x32) kwords sa55-sa58 1100xxxxx 128 (4x32) kwords sa59-sa62 1101xxxxx 128 (4x32) kwords sa63-sa66 1110xxxxx 128 (4x32) kwords sa67 111100xxx 32 kwords sa68 111101xxx 32 kwords sa69 111110xxx 32 kwords sa70 111111000 4 kwords sa71 111111001 4 kwords sa72 111111010 4 kwords sa73 111111011 4 kwords sa74 111111100 4 kwords sa75 111111101 4 kwords sa76 111111110 4 kwords sa77 111111111 4 kwords
52 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information sector protection the pl127j, pl129j, pl064j, and pl032j features several levels of sector protection, which can disable both the program and erase operatio ns in certain sectors or sector groups: persistent sector protection a command sector protection method that replac es the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a passwor d before changes to certain sec- tors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in sectors sa1-133, sa1-134, sa2-0 and sa2-1. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent se ctor protection mode. the customer must then choose if the persistent or password protection me thod is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the persistent sector protection method is desired, programming the persistent sector protection mode locking bit permanently sets the device to the persistent sector protection mode. if the password sector protection method is desired, programming the password mode locking bit per- manently sets the device to the password sector protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. one of the two modes must be selected when the device is first programmed. this prevents a program or virus from later set- ting the password mode locking bit, which woul d cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotect ed. optional spansion programming services en- able programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sector is pr otected or unprotected. see autoselect mode for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled prot ection method in previ- ous flash devices. this new method provides three different sector protection states: ta b l e 1 4 . sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 0 1 0 protected?ppb and dyb are changeable 1 0 0 1 1 0 0 1 1 protected?ppb not changeable, dyb is changeable 1 0 1 1 1 1
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 53 advance information ? persistently locked?the sector is protected and cannot be changed. ? dynamically locked?the sector is protected and can be changed by a simple command. ? unlocked?the sector is unprotected and can be changed by a simple command. to achieve these states, three types of ?bits? are used: ? persistent protection bit ? persistent protection bit lock ? persistent sector protec tion mode locking bit persistent protection bit (ppb) a single persistent (non-volatile) protection bi t is assigned to a maximum four sectors (see the sector address tables for specific sector protec tion groupings). all 4 kword boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individ- ually modifiable through the ppb write command. the device erases all ppbs in parallel. if any ppb requires erasure, the device must be instructed to preprogram all of the sector ppbs prior to ppb erasure. otherwise, a previously erased sector ppbs can potentially be over-erased. the flash device does not have a built-in means of prevent- ing sector ppbs over-erasure. persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock) is a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command se- quence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each se ctor. after power-up or hardware reset, the con- tents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cl eared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared st ate ? meaning the ppbs are changeable. when the device is first powered on the dybs po wer up cleared (sectors not protected). the pro- tection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs clea red, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the prot ected or unprotected state. these are the so-called dynamic locked or unlocked states. they are call ed dynamic states because it is very easy to switch back and forth between th e protected and unprotected conditions. this allows software to easily protect sectors against inadvertent change s yet does not prevent the easy removal of pro- tection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protecti on. the ppbs retain their state across power cycles because they are non-vo latile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing com- mands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of pr otection. once all ppbs are programmed to the de- sired settings, the ppb lock may be set to ?1?. se tting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the pp bs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are n eeded then the boot code can se t the ppb lock to disable any further changes to the ppbs during system operation.
54 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information the wp#/acc write protect pin adds a final level of hardware protection to sectors sa1-133, sa1- 134, sa2-0 and sa2-1. when this pin is low it is not possible to change the contents of these sectors. these sectors generally hold system boot code. the wp#/acc pin can prevent any changes to the boot code that co uld override the choices made while setting up sector protection during system initialization. for customers who are concerned about malicious vi ruses there is another level of security - the persistently locked state. to persistently protect a given sector or sector group, the ppbs associ- ated with that sector need to be set to ?1?. once all ppbs are programmed to the desired settings, the ppb lock should be set to ?1?. setting the ppb lock automa tically disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock ?freezes? the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. it is possible to have sectors that have been pe rsistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state ar e all unprotected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write com- mand for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power- cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppb s, and the device operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and protect the boot code by holding wp#/acc = vil. table 17 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb th en controls whether or not the sector is pro- tected or unprotected. if the user attempts to program or erase a prot ected sector, the device ignores the command and returns to read mode. a program command to a pr otected sector enables status polling for ap- proximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a prot ected sector enables stat us polling for approx- imately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. there is an alternative means of reading the protection status. take reset# to vil and hold we # at vih.(the high voltage a9 autoselect mode also works for reading the status of the ppbs). scanning the addresses (a18?a11) while (a6, a1, a0) = (0, 1, 0) will produce a logical ?1? code at device output dq0 for a protected sector or a ?0? for an unprotected sector. in this mode, the ot her addresses are don?t cares. address location with a1 = vil are reserved for autoselect manufacturer and device codes. persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guar- antee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 55 advance information password protection mode the password sector protection mode method allows an even higher level of security than the per- sistent sector protection mode. there are two main differen ces between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes ou t of a reset cycle, the ppb lock bit set to the locked state, rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwis e identical to the persis tent sector protection method. a 64-bit password is the only addition al tool utilized in this method. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along wi th a password. the flash device internally com- pares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash devi ce does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protecti on scheme, the customer must first program the password. the password may be co rrelated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. whil e programming in the password region, the cus- tomer may perform password verify operations. once the desired password is programmed in, th e customer must then set the password mode locking bit. this operation achieves two objectives: permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if no t carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prev ents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once pass- word mode locking bit is programmed, the persiste nt sector protection locking bit is disabled from programming, guaranteeing that no ch anges to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see ?p assword verify command?). the password func- tion works in conjunction with the password mo de locking bit, which when set, prevents the password verify command from re ading the contents of the passwo rd on the pins of the device.
56 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information write protect (wp#) the write protect feature provides a hardware me thod of protecting the upper two and lower two sectors without using v id . this function is provided by the wp# pin and overrides the previously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. if the system asserts v ih on the wp#/acc pin, the device reverts the upper two and lower two sectors to whether they were last set to be prot ected or unprotected. that is, sector protection or unprotection for these sectors depends on whet her they were last protected or unprotected using the method described in the high voltage sector protection . note that the wp#/acc pin must not be left floati ng or unconnected; inconsistent behavior of the device may result. persistent protection bit lock the persistent protection bit (ppb) lock is a vola tile bit that reflects the state of the password mode locking bit after power-up reset. if the pass word mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, th e only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bi t, allowing for sector ppbs modifications. as- serting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? wh en the password mode lock bit is not set. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for cleari ng the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent protection mode. high voltage sector protection sector protection and unprotection may also be implemented using programming equipment. the procedure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 1 for details on this procedure. note that fo r sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 57 advance information temporary sector unprotect this feature allows temporary unpro tection of previously protected sectors to change data in-sys- tem. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once figure 1. in-system sector protection/s ector unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 150 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 device failed remove v id from reset# write reset command sector protect complete device failed remove v id from reset# write reset command sector protect complete
58 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information v id is removed from the reset# pin, all the prev iously protected sectors are protected again. figure 2 shows the algorithm, and figure 21 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector unprotection mode. notes: 1. all protected sectors unprotected (if wp#/acc = vi l, upper two and lower two sectors will remain protected). 2. all previously protected sect ors are protected once again. figure 2. temporary sector unprotect operation secured silicon sector flash memory region the secured silicon sector feature provides a fl ash memory region that enables permanent part identification through an electronic serial numb er (esn) the 128-word secured silicon sector is divided into 64 factory-lockable words that can be programmed an d locked by the customer. the secured silicon sector is located at addresses 000000h-00007fh in both persistent protection mode and password protection mode. indicator bits dq6 and dq7 are used to indicate the fac- tory-locked and customer locked status of the part. the system accesses the secured silicon se ctor through a command sequence (see the enter se- cured silicon sector/exit secured silicon sector command sequence ). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sec- tor by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secured silicon sect or command sequence, or until power is removed from the device. on power-up, or following a hardware re set, the device reverts to sending commands to th e normal address space. note that the acc function and unlock bypass modes are not available when the se cured silicon sector is enabled. factory-locked area (64 words) the factory-locked area of the secured silicon se ctor (000000h-00003fh) is locked when the part is shipped, whether or not the area was progra mmed at the factory. the secured silicon sector factory-locked indicator bit (dq7) is permanentl y set to a ?1?. optional spansion programming services can program the factory-locked area wi th a random esn, a customer-defined code, or any combination of the two. because only spansion can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact your local sales office for details on using span sion?s programming services. note that the acc function and unlock bypass modes are not availabl e when the secured silicon sector is enabled. start perform erase or program operations reset# = v ih temporary sector unprotect completed ( note 2 ) reset# = v id (note 1)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 59 advance information customer-lockable area (64 words) the customer-lockable area of the secured sili con sector (000040h-00007fh) is shipped unpro- tected, which allows the customer to program and optionally lock the area as appropriate for the application. the secured silicon sector customer-l ocked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secured silicon protection bit program com- mand. the secured silicon sector can be read any number of times, but can be programmed and locked only once. note that the accelerated pr ogramming (acc) and unlock bypass functions are not available when programming the secured silicon sector. the customer-lockable secured silicon sector area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command sequence, and then fol - low the in-system sector protect algorithm as shown in figure 1 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon sector region without raising any device pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of th e secured silicon sector, follow the algorithm shown in figure 3 . once the secured silicon sector is locked and ve rified, the system must write the exit secured silicon sector region command sequence to retu rn to reading and writing the remainder of the array. the secured silicon sector lock must be used with caution since, once locked, there is no proce- dure available for unlocking the secured silicon se ctor area and none of the bits in the secured silicon sector memory space can be modified in any way. secured silicon sector protection bits the secured silicon sector protection bits prev ent programming of the secured silicon sector memory area. once set, the secured silicon sect or memory area contents are non-modifiable. figure 3. secured silicon sector protect verify write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
60 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information hardware data protection the command sequence requirement of unlock cycl es for programming or erasing provides data protection against inadvertent writes. in additi on, the following hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transi tions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper sign als to the control pins to prevent un- intentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce#, (ce1#, ce2# in pl129j) or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# (ce1# = ce2# in pl129j)= v ih or we# = v ih . to initiate a write cycle, ce# (ce1# / ce 2# in pl129j) and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# (ce1#, ce2# in pl129j) = v il and oe# = v ih during power up, the device does not accept commands on the risi ng edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification ou tlines device and host system software inter- rogation handshake, which allows specific vendor- specified software algorithms to be used for entire families of devices. software support ca n then be device-independent, jedec id-indepen- dent, and forward- and backward-compatible for th e specified flash device families. flash vendors can standardize their existing interf aces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to re ad array data. the system can read cfi informa- tion at the addresses given in ta b l e 1 5 to ta b l e 1 8 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is execut- ing an embedded program or embedded erase algorithm. the system can also write the cf i query command when the device is in the autoselect mode. the device enters the cfi query mode, and the sy stem can read cfi data at the addresses given in ta b l e 1 5 to ta b l e 1 8 . the system must write the reset comma nd to return the device to reading array data. for further information, please refer to the cfi sp ecification and cfi public ation 100. contact your local sales office for co pies of these documents.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 61 advance information ta b l e 1 5 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extend ed table (00h = none exists) ta b l e 1 6 . system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) ta b l e 1 7 . device geometry definition addresses data description 27h 0018h (pl127j) 0018h (pl129j) 0017h (pl064j) 0016h (pl032j) device size = 2 n byte 28h 29h 0001h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100)
62 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information 31h 00fdh (pl127j) 00fdh (pl129j) 007dh (pl064j) 003dh (pl032j) erase block region 2 information (refer to the cfi specification or cfi publication 100) 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100) ta b l e 1 8 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflect s modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h tbd address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h (plxxxj) sector protect/unprotect scheme 07 = advanced sector protection 4ah 00e7h (pl127j) 00e7h (pl129j) 0077h (pl064j) 003fh (pl032j) simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (plxxxj) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv table 17. device geometry definition (continued)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 63 advance information command definitions writing specific address and data commands or sequences into the comm and register initiates device operations. ta b l e 0 . 3 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a rese t command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens later. all data is latched on the rising edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens first. refer to the ac characteristic section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend co mmand, the corresponding bank enters the erase- suspend-read mode, after which the system can re ad data from any non-erase-suspended sector within the same bank. the system can read arra y data using the standard read timing, except that if it reads at an address within erase-suspend ed sectors, the device outputs status data. after completing a programming operation in the er ase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands sec- tion for more information. 4fh 0001h top/bottom boot sector flag 00h = uniform device, 01h = both top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h (pl127j) 0027h (pl129j) 0017h (pl064j) 000fh (pl032j) bank 1 region information x = number of sectors in bank 1 59h 0060h (pl127j) 0060h (pl129j) 0030h (pl064j) 0018h (pl032j) bank 2 region information x = number of sectors in bank 2 5ah 0060h (pl127j) 0060h (pl129j) 0030h (pl064j) 0018h (pl032j) bank 3 region information x = number of sectors in bank 3 5bh 0027h (pl127j) 0027h (pl129j) 0017h (pl064j) 000fh (pl032j) bank 4 region information x = number of sectors in bank 4 table 18. primary vendor-specific extended query (continued) addresses data description
64 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information after the device accepts a program suspend co mmand, the corresponding bank enters the pro- gram-suspend-read mode, after which the system can read data from any non-program- suspended sector within the same bank. see the program suspend/program resume commands for more information. the system must issue the reset command to return a ba nk to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the au- toselect mode. see the next section, reset command , for more information. see also requirements for reading array data in the device bus operations section for more in- formation. the ac characteristic table provides the read parameters, and figure 12 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se quence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to the read mode. once erasure begins, however, the device ig nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command se- quence before programming begins. this resets th e bank to which the system was writing to the read mode. if the program command sequence is wr itten to a bank that is in the erase suspend mode, writing the reset command returns that ba nk to the erase-suspend-read mode. once pro- gramming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se quence cycles in an autoselect command se- quence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the auto select mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mo de if that bank was in erase suspend and pro- gram-suspend-read mode if that bank was in pro-gram suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank ad dress and the autoselect command. the bank then enters the autoselect mode. the system may read any number of autoselect codes without rein- itiating the command sequence. ta b l e 0 . 3 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate ba nk address (ba) and sector address (sa). ta b l e 0 . 1 shows the address range and bank num ber associated with each sector. the system must write the reset command to retu rn to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend).
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 65 advance information enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secu red data area containing a random, eight word electronic serial number (esn). the system can a ccess the secured silicon sector region by is- suing the three-cycle enter secured silicon sect or command sequence. the device continues to access the secured silicon sector region until th e system issues the four-cycle exit secured sili- con sector command sequence. the exit secured silicon sector command sequence returns the device to normal operation. the secured silicon se ctor is not accessible when the device is exe- cuting an embedded program or embedded erase algorithm. ta b l e 0 . 3 shows the address and data requirements for both command sequences. see also ?secured silicon sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the se cured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writ- ing two unlock write cycles, followed by the pr ogram set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally gen- erated program pulses and verifies the programmed cell margin. ta b l e 0 . 3 shows the address and data requirements for the program command sequence. note that the secured silicon sector, au- toselect, and cfi functions are unavailable when a [program/erase] operation is in progress. when the embedded program algorithm is complete , that bank then retu rns to the read mode and addresses are no longer latched. the system can determine the status of the program oper- ation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the progra m operation. the program command sequence should be reinitiated once that bank ha s returned to the read mode, to ensure data in- tegrity. note that the secured silicon sector, au toselect and cfi functions are unavailable when the secured silicon sector is enabled. programming is allowed in any sequence and across sector boundaries. a bit cannot be pro- grammed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indica te the operation was successful. however, a suc- ceeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. the unlock by pass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass com- mand, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to progra m in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program ad- dress and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the st andard program command sequence, resulting in faster total programming time. ta b l e 0 . 3 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset com- mands are valid. to exit the unlock bypass mode , the system must issue the two-cycle unlock bypass reset command sequence. (see table 0.4) the device offers accelerated program operatio ns through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automati cally enters the unlock bypass mode. the system may then write the tw o-cycle unlock bypass program command sequence. the device
66 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information uses the higher voltage on the wp#/ac c pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 4 illustrates the algorithm for the program operation. refer to the erase/program opera- tions table in the ac characterist ics section for parameters, and figure 14 for timing diagrams. note: see table 0.3 for program command sequence. figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command . two additional unlock write cycles are then followed by the chip er ase command, which in turn invoke s the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these oper- ations. ta b l e 0 . 3 shows the address and data requir ements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad- dresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 67 advance information any commands written during the chip erase operation are ignored. note that secured silicon sector, autoselect, and cfi functions are unavai lable when a [program/e rase] operation is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence shou ld be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and figure 16 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sect or erase command sequence is initiated by writ- ing two unlock cycles, followed by a set-up co mmand. two additional unloc k cycles are written, and are then followed by the addr ess of the sector to be erased, and the sector erase command. ta b l e 0 . 3 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prio r to erase. the embedded erase algo- rithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector er ase time-out of 50 s occurs. during the time- out period, additional sector addresses and sect or erase commands may be written. loading the sector erase buffer may be done in any sequen ce, and the number of sectors may be from one sector to all sectors. the time between these addi tional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that pr ocessor interrupts be disabled during this time to ensure all commands are accept ed. the interrupts can be re-enabled after the last sector erase command is written. if any command other than 30h, b0h, f0h is input during the time- out period, the normal operat ion will not be guaranteed. the system must rewrite the com- mand sequence and any additi onal addresses and commands. note that secured silicon sector, autoselect, and cfi functions ar e unavailable when a [program/e rase] operation is in progress. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to read ing array data and ad- dresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system ca n determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase comm and sequence should be reinitiated once that bank has returned to reading arra y data, to ensure data integrity. figure 5 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ac characteristics section for parameters, and figure 16 section for timing diagrams.
68 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information notes: 1. see table 0.3 for erase command sequence. 2. see the section on dq3 for inform ation on the sector erase timer. figure 5. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the syst em to interrupt a sector erase operation and then read data from, or program data to, any se ctor not selected for erasure. the bank address is required when writing this command. this comma nd is valid only during the sector erase op- eration, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded pro- gram algorithm. when the erase suspend command is written during the sector erase operation, the device re- quires a maximum of 35 s to suspend the eras e operation. however, when the erase suspend command is written during the sector erase ti me-out, the device immediately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the de- vice ?erase suspends? all sectors selected for erasure.) reading at any address within erase- suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is acti vely erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend- read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 69 advance information in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is read y for another valid operation. refer to the secured silicon sector addresses and the autoselect command sequence sections for details. to resume the sector erase operation, the sy stem must write the erase resume command (ad- dress bits are don?t care). the bank address of th e erase-suspended bank is required when writing this command. further writes of the resume co mmand are ignored. another erase suspend com- mand can be written after the chip has resumed erasing. if the persistent sector protec tion mode locking bit is verifi ed as programmed without margin, the persistent sector protection mode locking bit program command should be reissued to im - prove program margin. if the secured silicon sector protecti on bit is verified as programmed without margin, the secured silicon sector protec tion bit program command should be reissued to improve program margin. ? after programming a ppb, two additional cycles are needed to de - termine whether the ppb has been programmed with margin. if the ppb has been programmed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. after erasing the ppbs, two additi onal cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been eras ed without margin, the er ase command should be reissued to improve the program margin. the prog ramming of either the ppb or dyb for a given sector or sector group can be verified by writ ing a sector protection status command to the device. note that there is no single command to inde pendently verify the programming of a dyb for a given sector group. program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming op- eration so that data can read from any non-suspended sector. when the program suspend command is written during a programming proces s, the device halts the programming operation within t psl (program suspend latency) and updates th e status bits. addresses are ?don?t-cares? when writing the program suspend command. af ter the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programmi ng operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secured silicon sector area, then user must use the proper command sequences to enter and exit this region. the sy stem may also write the autoselect command se- quence when the device is in program suspend mo de. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. see ?autoselect command sequen ce? for more information. after the program resume command is written, the device revert s to programming. the system can determine the status of the program operation using the dq7 or dq 6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system must write the pro- gram resume command (address bits are ?don?t care?) to exit the program suspend mode and continue the programming operation. further wr ites of the program resume command are ig- nored. another program suspend command can be written after the device has resumed programming.
70 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information command definitions legend: ba = address of bank switching to autoselect mode , bypass mode, or erase op eration. determined by pl127j: amax:a20, pl064j and pl129j: amax:a19, pl032j: amax:a18. pa = program address (amax:a0). addresses latch on falling edge of we# or ce# (ce1#/ce2# for pl129j) pulse, whichever happens later. pd = program data (dq15:dq 0) written to location pa. data latches on risi ng edge of we# or ce# (ce1#/ce2# for pl129j) pulse, whichever happens first. ra = read address (amax:a0). rd = read data (dq15:dq 0) from location ra. sa = sector address (amax:a12) for veri fying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific wr ite data. data latched on rising edge of we#. x = don?t care notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycl es. all other cycles are write operations. ta b l e 0 . 3 . memory array command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) addr data addr data addr data addr data addr data addr data read ( note 5 ) 1 ra rd reset ( note 6 ) 1 xxx f0 autoselect ( note 7 ) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 01 device id ( note 10 ) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e ( note 10 ) (ba) x0f ( note 10 ) secured silicon sector factory protect ( note 8 ) 4 555 aa 2aa 55 (ba) 555 90 x03 ( note 8 ) sector group protect verify ( note 9 ) 4 555 aaa 2aa 55 (ba) 555 90 (sa) x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( note 11 ) 1 ba b0 program/erase resume ( note 12 ) 1 ba 30 cfi query ( note 13 ) 1 55 98 accelerated program ( note 15 ) 2 xx a0 pa pd unlock bypass entry ( note 15 ) 3 555 aa 2aa 55 555 20 unlock bypass program ( note 15 ) 2 xx a0 pa pd unlock bypass erase ( note 15 ) 2 xx 80 xx 10 unlock bypass cfi (notes 13 , 15 ) 1 xx 98 unlock bypass reset ( note 15 ) 2 xxx 90 xxx 00
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 71 advance information 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (exc ept where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if pre- viously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is pro- viding status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see autoselect command sequence section for more information. 8. the data is dq6=1 for factory and custom er locked and dq7=1 for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10.device id must be read across cycles 4, 5, and 6. pl127j (x0eh = 2220h, x0fh = 2200h), pl129j (x0eh = 2221h, x0fh = 2200h),pl064j (x0eh = 22 02h, x0fh = 2201h), pl032j (x0eh = 220ah, x0fh = 2201h). 11.system may read and program in non-erasing sect ors, or enter autoselect mode, when in program/ erase suspend mode. program/eras e suspend command is valid only during a sector erase opera- tion, and requires bank address. 12.program/erase resume command is valid only during erase suspend mode, and requires bank ad- dress. 13.command is valid when device is ready to read array data or when device is in autoselect mode. 14.wp#/acc must be at v id during the entire operation of command. 15.unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array.
72 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information legend dyb = dynamic protection bit ta b l e 0 . 4 . sector protection command definitions command (notes) cycles bus cycles (notes 1 - 4 ) addr dat a addr dat a add r dat a addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit program (notes 5 , 6 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secured silicon protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (notes 5 , 7 , 8 ) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] password verify (notes 6 , 8 , 9 ) 4 555 aa 2aa 55 555 c8 pwa[0- 3] pwd[0- 3] password unlock (notes 7 , 10 , 11 ) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[ 1] pwd[ 1] pwa[ 2] pwd[ 2] pwa[ 3] pwd[ 3] ppb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa) wp 48 (sa)w p rd(0) ppb status 4 555 aa 2aa 55 555 90 (sa)wp rd(0) all ppb erase (notes 5 , 6 , 13 , 14 ) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)w p rd(0) ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status ( note 15 ) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write ( note 7 ) 4 555 aa 2aa 55 555 48 sa x1 dyb erase ( note 7 ) 4 555 aa 2aa 55 555 48 sa x0 dyb status ( note 6 ) 4 555 aa 2aa 55 555 58 sa rd(0) ppmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status ( note 5 ) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status ( note 5 ) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 73 advance information ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits amax:a12 uniquely select any sec- tor. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) x = don?t care ppmlb = password protec tion mode locking bit spmlb = persistent protec tion mode locking bit notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycl es. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (exc ept where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, progra m command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10.the password is written over four consecutive cycles , at addresses 0-3. 11.a 2 s timeout is required betw een any two portions of password. 12.a 100 s timeout is required between cycles 4 and 5. 13.a 1.2 ms timeout is required between cycles 4 and 5. 14.cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued an d verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15.dq1 = 1 if ppb locked, 0 if unlocked. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 19 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for dete rmining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algo - rithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence.
74 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro - grammed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is co mplete, the device outputs the da tum programmed to dq7. the sys - tem must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximatel y 1 s, then that bank re - turns to the read mode. during the embedded erase algorithm, data# po lling produces a ?0? on dq7. when the embed- ded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that ar e protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from th e complement to true da ta, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded pro- gram or erase operation, dq7 may change asyn chronously with dq15?dq 0 while output enable (oe#) is asserted low. that is, the device may ch ange from providing status information to valid data on dq7. depending on when the system samp les the dq7 output, it may read the status or valid data. even if the device has completed th e program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on successive read cycles. ta b l e 1 9 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algo- rithm. figure 18 in the ac characteristic section shows the data# polling timing diagram.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 75 advance information notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? be cause dq7 may change simultaneously with dq5. figure 6. data# polling algorithm ry / by # : r ead y / bu sy # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algo- rithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes program- ming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the bank s is in the erase-suspend-read mode. ta b l e 1 9 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
76 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation) , and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any ad- dress cause dq6 to toggle. the system may use ei ther oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm eras es the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog- gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, th e system can use dq7 (see the dq7: data# polling ). if a program address falls within a protected sect or, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-pr ogram mode, and stops toggling once the embed- ded program algorithm is complete. ta b l e 1 9 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 19 in read operation timings shows the toggle bit timing diagrams. figure 20 shows the differences between dq2 and dq6 in graphical form. see also the dq2: toggle bit ii .
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 77 advance information note: the system should recheck th e toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the dq6: toggle bit i and dq2: toggle bit ii for more information. figure 7. to g g l e b i t a l g o r i t h m dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system rea ds at addresses within those sect ors that have been selected for erasure. (the system may use either oe# or ce# (ce1# / ce2# for pl129j) to control the read cycles.) but dq2 cannot distinguish whether th e sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 9 to compare outputs for dq2 and dq6. figure 7 shows the toggle bit algorith m in flowchart form, and the dq2: toggle bit ii explains the algorithm. see also the dq6: toggle bit i . figure 19 shows the toggle bit timing diagram. figure 20 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. whenever th e system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is tog- gling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare th e new value of the toggle bit with the first. if the toggle bit is not togglin g, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va
78 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information however, if after the initial two read cycles, the sy stem determines that the toggle bit is still tog- gling, the system also should note whether the va lue of dq5 is high (see the section on dq5). if it is, the system should then determine again wh ether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high . if the toggle bit is no longer toggling, the device has successfully completed the program or eras e operation. if it is still toggling, the device did not completed the operation successfully, an d the system must write the reset command to return to reading array data. the remaining scenario is that the system initiall y determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through suc- cessive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determ ine the status of the operation (top of figure 7 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc - cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operatio n, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditio ns, the system must write the rese t command to return to the read mode (or to the erase-suspend-read mode if a ba nk was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the en tire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also the sector erase command sequence . after the sector erase command is written, the sy stem should read the status of dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure that th e device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 9 shows the status of dq3 relative to the other status bits.
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 79 advance information notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when readin g status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the sy stem must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. ta b l e 1 9 . write operation status status dq7 ( note 2 ) dq6 dq5 ( note 1 ) dq3 dq2 ( note 2 ) ry/ by # standard mode embedded program algorithm dq7# to g g l e 0 n/a no toggle 0 embedded erase algorithm 0 to g g l e 0 1 to g g l e 0 erase suspend mode erase- suspend-read erase suspended sector 1 no toggle 0 n/a to g g l e 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# to g g l e 0 n/a n/a 0 program suspend mode ( note 3 ) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) 1 reading within non-program suspended sector data data data data data 1
80 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground v cc ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v reset# ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v wp#/acc ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins reset#, and w p#/acc is ?0.5 v. during voltage transitions, wp#/ acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin reset# is +12.5 v which ma y overshoot to +14.0 v fo r periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v wh ich may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the sh ort circuit should not be greater than one second. 4. stresses above those listed un der ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other con- ditions above those indicated in the operational sectio ns of this data sheet is not implied. exposure of the device to absolute maximum rating conditio ns for extended periods may affect device reli- ability. operating ranges operating ranges define those limits between which the functionality of the device is guaranteed. industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?55c to +125c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7?3.6 v v io (see note) . . . . . . . . . . . . 1.65?1.95 v (for pl127j and pl129j) or 2.7?3.6 v (for all plxxxj devices) notes: for all ac and dc specifications, v io = v cc ; contact your local sales office for other v io options. figure 8. maximum overshoot waveforms 20 ns 20 ns +0.8 ?0.5 v 20 ns ?2.0 20 ns 20 ns v cc +2.0 v cc +0.5 v 20 ns 2.0 v maximum negative overshoot waveform maximum positive overshoot waveform
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 81 advance information dc characteristics notes: 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v ccmax . 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 1 m a. 5. not 100% tested. 6. in s29pl129j there are two ce# (ce1#, ce2#). ta b l e 2 0 . cmos compatible parameter symbol parameter description test conditions min ty p max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) oe# = v ih , v cc = v cc max (note 1) 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current (notes 2 , 3 ) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current ( note 2 ) ce#, reset#, wp#/acc = v io 0.3 v 0.2 5 a i cc4 v cc reset current ( note 2 ) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v io 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc7 v cc active read-while-erase current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc8 v cc active program-while-erase- suspended current (notes 2 , 5 ) oe# = v ih 17 25 ma i cc9 v cc a c t i v e pa g e re a d c u r r e n t ( note 2 ) oe# = v ih , 8 word page read 10 15 ma v il input low voltage v io = 1.65?1.95 v (pl127j and pl129j) ?0.4 0.4 v v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 1.65?1.95 v (pl127j and pl129j) v io ?0.4 v io +0.4 v v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = 1.65?1.95 v (pl127j and pl129j) 0.1 v i ol = 2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 0.4 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = 1.65?1.95 v (pl127j and pl129j) v io ?0.1 v i oh = ?2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 2.4 v v lko low v cc lock-out voltage ( note 5 ) 2.3 2.5 v
82 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information 7. valid ce1#/ce2# conditions: (ce1# = v il, ce2# = v ih, ) or (ce1# = v ih, ce2# = v il ) or (ce1# = v ih, ce2# = v ih ). ac characteristic test conditions note: diodes are in3064 or equivalent. figure 9. test setups ta b l e 2 1 . test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v io = 1.8 v (pl127j and pl129j) 5 ns v io = 3.0 v input pulse levels v io = 1.8 v (pl127j and pl129j) 0.0 - 1.8 v v io = 3.0 v 0.0?3.0 input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v 2.7 k ? c l 6.2 k ? 3.6 v device under te s t c l device under te s t v io = 3.0 v v io = 1.8 v (pl127j and pl129j)
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 83 advance information switching waveforms vcc ramprate all dc characteristics are specified for a v cc ramp rate > 1v/100 s and v cc >=v ccq - 100 mv. if the v cc ramp rate is < 1v/100 s, a hardware reset required.+ table 22. key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 10. input waveforms and measurement levels vio 0.0 v vio/2 vio/2 output measurement level in
84 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information read operations notes: 1. not 100% tested. 2. see figure 9 and table 21 for test specifications 3. measurements performed by placing a 50 ohm te rmination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. s29pl129j has two ce# (ce1#, ce2#). 5. valid ce1# / ce2# conditions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) or (ce1# = v ih, ce2# = v ih ). 6. valid ce1# / ce2# transitions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) to (ce1# = ce2# = v ih ). 7. valid ce1# / ce2# transitions: (ce1# = ce2# = v ih ) to (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ). 8. for 70pf output load capacitance, 2 ns will be added to the above t acc ,t ce ,t pacc ,t oe values for all speed grades. ta b l e 2 3 . read-only operations parameter description te s t s e t u p speed options jedec std. 55 60 65 70 unit t avav t rc read cycle time ( note 1 ) min 55 60 65 70 ns t avqv t acc address to output delay ce#, oe# = v il max 55 60 65 70 ns t elqv t ce chip enable to output delay oe# = v il max 55 60 65 70 ns t pacc page access time max 20 25 25 30 ns t glqv t oe output enable to output delay max 20 25 30 ns t ehqz t df chip enable to output high z ( note 3 ) max 16 ns t ghqz t df output enable to output high z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first ( note 3 ) min 5 ns t oeh output enable hold time ( note 1 ) read min 0 ns toggle and data# polling min 10 ns
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 85 advance information notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 11. read operation timings notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 12. page read operation timings t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df amax - a3 ce# oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pacc t pacc t pacc
86 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information reset note: not 100% tested. ta b l e 2 4 . hardware reset (reset#) parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode ( see note ) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode ( see note ) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read ( see note ) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the below waveform ce# = ce1# or ce2# figure 13. reset timings reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 87 advance information erase/program operations notes: 1. not 100% tested. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). 4. see the ?erase and programming performance? section for more information. ta b l e 2 5 . erase and program operation parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time ( note 1 ) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 ns t aht a d d r e s s h o l d t i m e f r o m c e # ( c e 1 # , c e # 2 i n pl 1 2 9 j ) or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 25 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# (ce1# or ce#2 in pl129j) setup time min 0 ns t wheh t ch ce# (ce1# or ce#2 in pl129j) hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 20 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation ( note 4 ) ty p 6 s t whwh1 t whwh1 accelerated programming operation ( note 4 ) ty p 4 s t whwh2 t whwh2 sector erase operation ( note 4 ) ty p 0.5 sec t vcs v cc setup time ( note 1 ) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns min 35 ns t psl program suspend latency max 35 s
88 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information timing diagrams notes: 1. pa = program address, pd = program data, d out is the true data at the program address 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 14. program operation timings figure 15. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or t vhh
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 89 advance information notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status? 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 16. chip/sector erase operation timings figure 17. back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as
90 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information note: va = valid address. illustration shows first st atus cycle after command sequence, last status read cycle, and array data read cycle. figure 18. data# polling timings (during embedded algorithms) notes: 1. va = valid address; not required for dq6. illust ration shows first two status cycle after command sequence, last status read cycle, and array data read cycle 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 19. toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 91 advance information protect/unprotect note: not 100% tested. note: dq2 toggles only when read at an address with in an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 ta b l e 2 6 . temporary sector unprotect parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s figure 21. temporary sector unprotect timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
92 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information controlled erase operations notes: 1. not 100% tested. 2. see the ?erase and program operation? section for more information. notes: 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 22. sector/sector block protect a nd unprotect timing diagram ta b l e 2 7 . alternate ce# controlled erase and program operations parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time ( note 1 ) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 ns t dveh t ds data setup time min 25 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# (ce1# or ce#2 in pl129j) pulse width min 35 40 ns t ehel t cph ce# (ce1# or ce#2 in pl129j) pulse width high min 20 25 ns t whwh1 t whwh1 programming operation ( note 2 ) ty p 6 s t whwh1 t whwh1 accelerated programming operation ( note 2 ) ty p 4 s t whwh2 t whwh2 sector erase operation ( note 2 ) ty p 0.5 sec sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 93 advance information note: this parameter is defined for ce1#/ce2# recover time for read/read, program/read, and read/ program operations. program/program operation are not allowed and only a single program operation is allowed at one time. notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of th e data written to the device. d out is the data written to the device 4. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 5. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 23. alternate ce# controlled writ e (erase/program) operation timings ta b l e 2 8 . ce1#/ce2# timing (s29pl129j only) parameter description all speed options unit jedec std t ccr ce1#/ce2# recover time ( note ) min 0 ns figure 24. timing diagram for alternating between ce1# and ce2# control t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy ce1# t ccr t ccr ce2#
94 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerb oard pattern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum pr ogram times listed. 4. in the pre-programming step of the embedded er ase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 0.3 for further information on command definitions. 6. the device has a minimum erase and prog ram cycle endurance of 100,000 cycles. ta b l e 2 9 . erase and programming performance parameter ty p ( note 1 ) max ( note 2 ) unit comments sector erase time 0.5 2 sec excludes 00h programming prior to erasure ( note 4 ) chip erase time pl127j/129j 135 216 sec pl064j 71 113.6 sec pl032j 39 62.4 sec word program time 6 100 s excludes system level overhead ( note 5 ) accelerated word program time 4 60 s chip program time ( note 3 ) pl127j/129j 50.4 200 sec pl064j 25.2 50.4 sec pl032j 12.6 25.2 sec
publication number s71pl-jb0_00 revision a amendment 0 issue date april 21, 2005 advance information type 2 psram d-die 32mbit (2m word x 16-bit) features ? process technology: cmos ? organization: 2m x16 bit ? power supply voltage: 2.7~3.1v ? three state outputs ? compatible with low power sram ? support 4 page read mode ? initial access time: 70 ns pin description pin name description i/o cs1#, cs2 chip select i oe# output enable i we# write enable i lb#, ub# lower/upper byte enable i a0-a20 address inputs i i/o0-i/o15 data inputs/outputs i/o v cc /v ccq power supply ? v ss /v ssq ground ? dnu do not use ?
96 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information power up sequence 1. apply power. 2. maintain stable power (v cc min.=2.7v) for a minimum 200 s with cs1#=high or cs2=low. timing diagrams power up notes: 1. after v cc reaches v cc (min.), wait 200 s with cs1# high. then th e device gets into the normal operation. figure 25. power up 1 (cs1# controlled) min. 200 s v cc cs 1# cs2 v cc(min) normal operation power up mode
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 97 advance information notes: 1. after v cc reaches v cc (min.), wait 200 s with cs2 low. then th e device gets into the normal operation. functional description legend: x = don?t care (must be low or high state). figure 26. power up 2 (cs2 controlled) mode cs1# cs2 oe# we# lb# ub# i/o 1-8 i/o 9-16 power deselected h x x x x x high-z high-z standby deselected x l x x x x high-z high-z standby deselected x x x x h h high-z high-z standby output disabled l h h h l x high-z high-z active outputs disabled l h h h x l high-z high-z active lower byte read l h l h l h d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l h x l l h d in high-z active upper byte write l h x l h l high-z d in active word write l h x l l l d in d in active min. 200 s v cc cs1# cs2 v cc(min) normal operation power up mode
98 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information absolute maximum ratings notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. functional operation should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than one second may affect reliability. dc recommended operating conditions notes: 1. ta=-40 to 85c, unless otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc +0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c storage temperature t stg -65 to 150 c symbol parameter min ty p max unit v cc power supply voltage 2.7 2.9 3.1 v v ss ground 0 0 0 v ih input high voltage 2.2 ? v cc + 0.3 (note 2) v il input low voltage -0.2 (note 3) ? 0.6 symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c io input/output capacitance v out = 0v ? 10 pf
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 99 advance information dc and operating characteristics notes: 1. standby mode is supposed to be set up after at least one active operation after power up. i sb1 is measured after 60 ms from th e time when standby mode is set up. ac operating conditions test conditions (test load and test input/output reference) ? input pulse level: 0.4 v to 2.2 v ? input rising and falling time: 5ns ? input and output reference voltage: 1.5v ? output load (see figure 27): 50pf note: including scope and jig capacitance. item symbol test conditions min ty p max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs#=v ih , zz# = v ih , oe# = v ih , or we# = v il , v io = v ss to v cc -1 ? 1 a average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs# 0.2v, zz# v cc -0.2v, v in 0.2v or v in v cc -0.2v ?? 7 ma i cc2 cycle time=t rc + 3t pc , i io = 0ma, 100% duty, cs# = v il , zz# = v ih , v in = v il or v ih ?35ma output low voltage v ol i ol =2.1ma ? ? 0.4 v output high voltage v oh i oh =-1.0ma 2.4 ? ? v standby current (cmos) i sb1 ( note 1 ) cs# v cc - 0.2v, zz# v cc - 0.2v, other inputs = v ss to v cc ??100a figure 27. output load c l dout
100 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information ac characteristics (ta = -40c to 85c, v cc = 2.7 to 3.1 v) notes: 1. t wp (min)=70 ns for continuous write operation over 50 times. symbol parameter speed bins unit 70ns min max read t rc read cycle time 70 ? ns t aa address access time ? 70 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 70 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 10 ? ns t olz output enable to low-z output 5 ? ns t hz chip disable to high-z output 0 25 ns t bhz ub#, lb# disable to high-z output 0 25 ns t ohz output disable to high-z output 0 25 ns t oh output hold from address change 3 ? ns t pc page cycle time 25 ? ns t pa page access time ? 20 ns write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t as address set-up time 0 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 ( note 1 ) ? ns t wr write recovery time 0 ? ns t whz write to output high-z 0 25 ns t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns t ow end write to output low-z 5 ? ns
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 101 advance information timing diagrams read timings notes: 1. address contro lled, cs1#=oe#=v il , we#=v ih , ub# and/or lb#=v il . notes: 1. we#=v ih . figure 28. timing waveform of read cycle(1) figure 29. timing waveform of read cycle(2) address data out previous data valid data valid t aa t rc t oh data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address ub#, lb# oe# data out cs1# cs2
102 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information notes: 1. t hz and t ohz are defined as the time at which the outp uts achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. 3. t oe (max) is met only when oe# becomes enabled after t aa (max). 4. if invalid address signals shorter than min. t rc are continuously repeated for over 4s, the device needs a normal read timing (t rc ) or needs to sustain standby state for min. t rc at least once in every 4s. write timings figure 30. timing waveform of page cycle (page mode only) figure 31. write cycle #1 (we# controlled) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa high z a1~a0 dq15~dq0 oe# t ohz t oe t co t aa cs1# cs2 address 1) address cs1# data undefined ub#, lb# we# data in data out t wc t cw t wr t aw t bw t wp t as t dh t dw t whz t ow high-z high-z data valid cs2
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 103 advance information figure 32. write cycle #2 (cs1# controlled) figure 33. timing waveform of write cycle(3) (cs2 controlled) address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp t dh t dw t wr t as cs1# cs2 address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp(1) t dh t dw t wr t as cs1# cs2
104 s71pl-jb0 based mcps s71pl-jb0_00_a0 april 21, 2005 advance information notes: 1. a write occurs during the overlap (t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte operation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs1# or we# going high. figure 34. timing waveform of write cycle(4) (ub#, lb# controlled) address data valid ub #, lb# we# data in data out high-z t wc t cw t bw t wp t dh t dw t wr t aw t as cs1# cs2
april 21, 2005 s71pl-jb0_00_a0 s71pl-jb0 based mcps 105 advance information revision summary revision a (april 21, 2005) initial release. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear re action control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon sy stem), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex - port under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government en tity will be required for export of those products. trademarks and notice the contents of this document are subject to change without noti ce. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assu mes no liability for any damages of any kind arising out of the use of the informatio n in this document. copyright ?2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for identification purpose s only and may be trademarks of their respective companies.

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